Method and apparatus for DLL lock latency detection

Details Method and apparatus for DLL lock latency detection Method and apparatus for DLL lock latency detection

2005-02-22

2005-02-22

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06859413

ABSTRACT:
Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

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