Method and apparatus for dividing a high-frequency clock...

Details Method and apparatus for dividing a high-frequency clock... Method and apparatus for dividing a high-frequency clock...

2005-09-27

2005-09-27

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000, C713S502000

Reexamination Certificate

active

06950958

ABSTRACT:
A method including frequency dividing a high-frequency clock signal into a divided frequency, and further dividing the divided frequency into another divided frequency in accordance with a data input (DIN).

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Foroudi et al., Low-voltage low-power topology for high-speed applications, 2001, IEEE, pp. 135-138.
Nelson Victor P et al., Digital Logic Circuit Analysis and Design, 1995, Prentice Hall Inc., pp. 449-477.

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