Method and apparatus for dividing a digital signal by X.5 in...

Details Method and apparatus for dividing a digital signal by X.5 in... Method and apparatus for dividing a digital signal by X.5 in...

2006-01-25

2008-10-28

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000, C327S115000, C327S117000, C377S047000, C377S048000

Reexamination Certificate

active

07444534

ABSTRACT:
An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divider methodology permits the design of advanced circuit functions, such as double data rate memory operations, without the need for additional clock signal sources.

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GRAF—Divide by 1-1/2 Circuit—downloaded Oct. 6, 2005 from DesignNotes.com.

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