Method and apparatus for diverting void diffusion in...

Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – In integrated circuit

Reexamination Certificate

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C257S334000, C257S396000, C257S503000, C257SE21170, C257SE21532, C257SE21585

Reexamination Certificate

active

07436040

ABSTRACT:
A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

REFERENCES:
patent: 4826455 (1989-05-01), Case et al.
patent: 6537097 (2003-03-01), Szu
patent: 7142395 (2006-11-01), Swanson et al.
T.C. Huang et al.; “Numerical Modeling and Characterization of the Stress Migration Behavior Upon Various 90 nanometer Cu/Low k Interconnects”; Jun. 2-4, 2003; 4 pages.
Derryl D. J. Allman et al.; “Method And Apparatus For Redirecting Void Diffusion Away From Vias In An Integrated Circuit Design”; Patent Application, 20 pages, Dec. 29, 2005.

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