Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1999-08-06
2004-06-22
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C713S400000, C713S500000, C713S501000
Reexamination Certificate
active
06754745
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to distributing a clock in a network; more particularly, the present invention relates to generating a reference clock and supplying the reference clock throughout the network for synchronizing clocks.
BACKGROUND OF THE INVENTION
Synchronization of today's digital networks is essential to reliable transport of delay sensitive services such as voice and video. Network Synchronization prevents impairments that could result in unreliable and/or unpredictable service performance. These impairments include jitter, wander, and phase transients.
Jitter is a short term variation of the significant instants of a digital signal from their ideal position in time, where short term refers to phase oscillations with spectral components greater or equal to 10 Hertz. jitter can adversely affect the ability of digital equipment to correctly sample an incoming bit stream or lead to overflows or underflows in its buffers. Several factors contribute to jitter generation and accumulation throughout the network. For example, signals passing through repeaters accumulate jitter due to imperfections in timing circuits. Jitter is also generated by multiplexers during bit stuffing/removal process to accommodate frequency differences.
Wander is a long term variation of the significant instants of a digital signal from their ideal position in time, where long term refers to phase oscillations with spectral components less than 10 hertz. Clocks average the characteristics of their reference over a period of time to develop an estimate of the reference. Wander causes inaccuracies in this estimate. Wander is mostly generated by and/or contributed to the asynchronous nature of mapping lower speed DSx signals into higher speed SONET frames that require occasional payload pointer adjustments. Wander is also caused by effects of temperature variations on transmission media.
Phase transients is a large and sudden change in phase of a signal. Phase transients are caused by hardware protection switching of primary and secondary clock sources or by payload pointer adjustments in SONET.
Jitter, wander, and phase transients cause frame slips. Repetition or deletion of a complete frame is called a “controlled slip”. An “uncontrolled slip” is a disruption in a framing pattern that causes frame alignments. Several studies have been conducted to measure the effects of these impairments on applications.
A purpose of clock synchronization is to prevent slips in a digital network. Slips are a disruption in the data flow due to an overflow or underflow of a buffer due to variations in read and write rates.
In a standard system, the data is written into a buffer at the same rate as it is read. Since the read and write rates are dependent on two separate clocks, if the clocks are not synchronized, the read and write rates differ and slips occur. For example, if the read clock is 1.544000 MHz, the write clock is 1.544001 MHz and the buffer is 1 frame (193 bits), then a slip, in this case an over run, occurs after 193 seconds. The larger the buffer is, the longer it takes for a slip to occur, but it will eventually happen.
There are basically two modes of clocking defined as BITS and Line.
FIG. 1
illustrates a BITS clocking system for GR-1244. See Clocks for Synchronized Network: Communication Generic Criteria, GR-1244-Core, issue 1, January 1995; GR-1244-ICR, issue 1A, December 1996; Synchronous Optical Network (SONE-T) Transport Systems: Communication Generic Criteria, GR-253-CORE, issue 2, December 1995 and Rev. 2, January 1999; GR-253-ICR, issue 2C, Feb. 1, 1999. Referring to
FIG. 1
, the basic clock system for GR-1244 consists of two redundant inputs, which are 3 wire wrap terminals, that are properly terminated and then fed to redundant clock circuits. Each of the redundant paths includes holdover circuitry that has access to the other path. Each holdover circuitry provides a clock to synchronization circuitry. A Stratum clock from a Stratum clock source (e.g., a local oscillator) is also sent to the synchronization circuitry and is used in the absence of a clock at the input of the clock system. The clock monitor includes circuits that monitor the quality of the clock, causes the synchronization circuitry to synchronize the input clock to the system clock requirement, and provides control for switchover circuitry in case of failure of either input or clock circuitry. The output of the switch over is provided to the system.
FIG. 2
illustrates an ideal line clock system. Referring to
FIG. 2
, the line clock system for GR-1244 consists of two active inputs providing clocking for all outputs through a line interface unit (LIU), where any port on the system can be used as primary and any other as secondary clock source. These clocks are then used for the transmit clock on all interfaces.
Clocks are distributed through various systems using a hierarchical system. Clocks distributed in this way are commonly referred to as Stratum clocks. In a Stratum Hierarchy, there are four defined levels of hierarchy called PRS or Level 1 through Level 4 where Level 1 is the most precise and Level 4 is the least precise. Table 1 below illustrates the Stratum Hierarchy.
TABLE 1
Stratum Hierarchy
Level
PPM Rating
Holdover
Filtering
1
0.000001
2
0.0016
Yes
.01 hz
3e
4.6
Yes .001 ppm
.01 Hz
3
4.6
Yes .37 ppm
No
SMC
20
No
.1 Hz
4e
32
No
No
4
32
No
No
In the Stratum hierarchy, Level 1, also known as Primary Reference Clock (PRS), is the most precise and accurate clock available. These clocks are atomic oscillator or GPS based and are used to generate all other clocks used in the network. Each lower level of the hierarchy is supplied by a higher or same level clock source.
FIG. 3
illustrates an example of the Stratum hierarchy.
In actual implementation, it is necessary to avoid clock loops where multiple units at the same stratum level are connected in a loop. This condition generally occurs when a primary reference to a node fails and the secondary reference is not connected back to a PRS source.
FIG. 4
illustrates a loop condition. Referring to
FIG. 4
, node
3
uses node
2
as the primary source and node
7
as the secondary. While node
2
is operational, nodes
3
-
7
are using the PRS clock from node
1
. However, when node
2
fails, node
3
switches to using node
7
as the backup clock source and a timing loop is created.
In most implementations of a network, a PRS source is used to clock a master Timing Signal Generator (TSG) which then uses DS
1
s to drive slave TSGs. All network elements in a Central Office are then tied to the master TSG in various ways, thus providing a PRS traceable clock to all interfaces.
In order to obtain a common clock to be used among many network elements, some form of clock recovery is necessary. One of multiple forms of clocking may be used and includes Synchronous Residual Time Stamp (SRTS) clock recovery, adaptive clocking and adaptive data.
The SRTS clock recovery requires that a network clock be provided to customer premises equipment (CPE) in a network, such as an access network. The SRTS method uses a Residual Time Stamp (RTS) to measure and convey information about the frequency difference between a common reference clock derived from the network and a service clock. The same derived network clock is assumed to be available at both the transmitter and the receiver. One problem associated with employing the SRTS method is that the CPE must be redesigned to accommodate it.
Adaptive clocking requires the transmit clock be adjustable based on thresholds in a FIFO. The adaptive clock method is a general method for source clock frequency recovery in a network in which no explicit timing information of the source clock is transported by the network. The method is based on the fact that the amount of transmitted data is an indication of the source frequency, and this information can be used at the receiver to recover the source clock frequency. By averaging the amount of received data over a period of time, CDV (Cell
Abkarian Alfred
Haydt Richard
Horvath Alexander
Accelerated Networks
Blakely , Sokoloff, Taylor & Zafman LLP
Farood Mohammad O.
Gaffin Jeffrey
LandOfFree
Method and apparatus for distributing a clock in a network does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for distributing a clock in a network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for distributing a clock in a network will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3355446