Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2001-02-16
2004-06-22
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C713S500000
Reexamination Certificate
active
06754748
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to communications on a single chip, and more particularly, to methods and apparatus for distributing multi-source/multi-sink control signals among various nodes on a chip.
BACKGROUND OF THE INVENTION
Address and data busses provide data paths that are shared by a number of data processing devices, such as memory devices, micro-controllers, microprocessors, digital signal processors (DSPs) and peripheral devices. Busses are typically formed on printed circuit boards (PCBs) and interconnect the various devices mounted on the PCB. The busses may also extend to connectors in order to allow external devices to be coupled to the bus.
Recently, integrated circuit (IC) manufacturers have begun producing single chips containing multiple device cores, such as multiple memory devices, micro-controllers, microprocessors and digital signal processors (DSPs), that were traditionally mounted on a PCB and interconnected by one or more busses on the PCB. Such a single chip is commonly referred to as a system-on-a-chip (SoC). SoCs incorporate one or more busses to provide data paths to interconnect the multiple core devices on the chip, often referred to as “nodes.” The busses on SoCs, however, comprise conductor traces on the chip and thus tend to be much shorter in length and less sensitive to noise than PCB busses.
As SoCs grow in size and complexity, it becomes increasingly difficult to communicate control signals among the various nodes on the SoC, primarily due to the resistive-capacitive (RC) delays attributed to the conductor length. Within each node on the SoC, increasing clock rates can be achieved using phase locked loop (PLL) or digital delay line (DDL) circuits (or both). It is also highly desirable to perform inter-node communications at the same internal clock rate used by each node.
FIG. 1
is a schematic block diagram illustrating a conventional SoC
100
having a bus
110
that interconnects the various nodes
120
-
1
through
120
-N (multiple core devices), collectively referred to as nodes
120
, on the chip
100
. As previously indicated, the nodes
120
may be embodied, for example, as memory devices, micro-controllers, microprocessors and digital signal processors (DSPs).
When an SoC
100
includes multiple nodes
120
communicating over a common bus
110
, an Arbiter
150
is often used to determine which node
120
should actively drive the bus
110
at a particular time. Multi-source/multi-sink control signals, such as acknowledgement (ACK), data-valid, interrupt and error signals, are often employed to control communications on the SoC bus
110
. All of the various nodes
120
and the Arbiter
150
typically operate synchronously with respect to a common clock
160
, and ideally transfers on the bus would occur within one clock period.
When a given node
120
desires to communicate on the common bus
110
, the node
120
sends a unidirectional request signal (REQn) to the Arbiter
150
, and receives back a unidirectional grant signal (GNTn) from the Arbiter
150
that allows the node
120
to drive onto the bus wires in the next cycle. One condition for getting a GNTn signal is that the receiving node
120
-R that is to receive the data has signaled to the Arbiter
150
that the receiving node
120
-R is ready to accept data. After the GNTn has been received, the transmitting node
120
-T drives data onto the bus and looks for an ACK signal from the receiving node
120
-R indicating that the initial data has been received and that more data can be sent. The ACK signal is an example of a multi-source/multi-sink network.
Under control of the Arbiter
150
, one of the nodes
120
will drive the ACK signal and another node
120
will monitor the ACK signal. The ACK signal transmits information from any node
120
to any other node
120
over an ACK network in one clock period. The ACK signal must also return to an inactive state when no nodes
120
are using the bus. The implementation of the ACK network (and the distribution network for other multi-source/multi-sink control signals) requires the network to be returned to an inactive state if there is no active driver.
A number of techniques have been proposed or suggested for distributing multi-source/multi-sink control signals among various nodes
120
on a chip
100
. Such multi-sourced networks are defined to be wired-OR or wired-AND circuits, and are commonly implemented with common-source or common-drain drivers using CMOS technology. A typical example is the interrupt signal (INT) of a microprocessor chip on a PCB sourced by several other chips. On the PCB, a single resistor pulls the INT network to the power supply voltage (V
DD
) when all drivers are inactive. A driver may pull the INT signal towards V
SS
by turning on a transistor connected in the common-source mode. In the PCB environment, all drivers act independently and there is only one device monitoring the state of the INT network, but it is easily extended to an SoC example.
In the SoC environment of the present invention, the wired-OR technique discussed above may be attempted with a passive resistor or an active transistor.
FIG. 2A
illustrates a passive resistor implementation, where a pull-up resistor
215
may be located off of the SoC
210
(since high tolerance resistors are difficult to build on-chip) and connected to the wired-OR network
220
through a bond pad
225
. Alternatively, the resistor could be implemented as either a strong always-on transistor and/or an active clamp transistor.
FIGS. 2B and 2C
illustrate active transistor implementations, where transistors
260
,
280
may be located on of the SoC
250
,
270
itself and connected to the wired-OR network
255
,
275
. For active transistor implementations, the strength of the pull-up device
260
,
280
must be matched to the load and configuration of the wired-OR network
255
,
275
such that the signal may be pulled down to V
SS
and restored to V
DD
in one clock period. A wired-AND solution would use complementary devices and supplies to those shown in
FIGS. 2A-2C
.
Generally, each control signal must be brought to a known state before a given device can drive the signal. In the implementation of
FIGS. 2A through 2C
, the pull-up devices
215
,
260
,
280
will return the signal state to a known, inactive state when no individual node
120
is driving the signal. Thereafter, an individual receiving node
120
-R desiring to send an ACK signal must bring the ACK control line high to acknowledge receipt of data, and once the transmitting node
120
-T receives the ACK signal, the receiving node
120
-R must return the ACK line to a low state. However, such arrangements are not power efficient, and it is hard for a single node
120
on an SoC
210
,
250
,
270
to pull down the signal against the pull-up devices
215
,
260
,
280
. In addition, the strength of the pull-up devices
215
,
260
,
280
in such implementations must be adjusted for process variations and operating conditions. Furthermore, the wired-OR and wired-AND techniques exhibit static power dissipation whenever the multi-source/multi-sink control signal is asserted. Finally, segments of the wired-OR network closest to the pull-up device will not be pulled to zero, reducing noise margins, particularly for low voltage operation.
A need therefore exists for an improved distribution network for multi-source/multi-sink control signals. A further need exists for a control signal distribution network that increases the information transfer rate. Yet another need exists for a control signal distribution network that provides improved scalability.
SUMMARY OF THE INVENTION
Generally, a method and apparatus are disclosed for distributing multi-source/multi-sink control signals in one clock period among a number of nodes on a chip. According to one aspect of the invention, each node assists in returning the control signal to an inactive state at the start of each cycle. Thus, since all nodes contribute to returning the control signal to the inactive sta
Fernando John Susantha
Lee Hyun
Little Trevor Edward
Agere Systems Inc.
Ray Gopal C.
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