Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-01-06
2000-08-29
Peikari, B. James
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711135, 711156, 711165, 711173, 711202, 711213, 712200, 712204, G06F 942
Patent
active
061122807
ABSTRACT:
There is disclosed a dynamic cache which is divided into sections, or chunks, for the storage of optimized code. The optimized code may contain pointers to code in other chunks. When a cache chunk is to be reused, then the pointers to other caches, as well as the pointers from other caches to code contained with the cache that is to be removed, are changed to point to either code contained in a victim chunk of the cache, or, alternatively, to point back to the translator. The system can dynamically change the number and size of the cache chunks and the number and size of the victim chunks, if any.
REFERENCES:
patent: 4382278 (1983-05-01), Appelt
patent: 5354232 (1994-10-01), Pontow
patent: 5404500 (1995-04-01), Legvold et al.
patent: 5420993 (1995-05-01), Smith et al.
patent: 5870576 (1999-02-01), Faraboschi et al.
"Garbage Collection Algorithms for Automatic Dynamic Memory Management" by Richard Jones and Rafael Lins; Copyright 1996 by John Wiley & Sons Ltd., England; cover page; inside cover page; pp. 143-152.
Buzbee William B.
Mattson, Jr. James S.
Shah Lacky V.
Hewlett--Packard Company
Peikari B. James
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