Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer
Reexamination Certificate
1999-09-02
2003-09-30
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Frame buffer
C345S539000, C345S546000
Reexamination Certificate
active
06628291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved data processing system and, in particular, to an improved method and apparatus for refreshing a display. Still more particularly, the present invention provides a method and apparatus for refreshing a display from data in multiple frame buffers.
2. Description of Related Art
In displaying images in a data processing system, a complete image on a display device is formed from a frame, which contains all of the pixels making up the image displayed on the display device. Typically, the pixels for a frame are stored as a matrix of pixels in which the pixels are displayed one line at a time. The entire image is scanned out sequentially by a video controller one line at a time. This scanning is typically performed from the top of the display to the bottom of the display and then back up to the top of the display. The image displayed is typically stored in a buffer, also referred to as a frame buffer. In single port video memories, a screen refresh occurs by reading the pixel data from the memory to send it to a digital to analog converter (DAC) for conversion to analog signals on the display. Such a mechanism is straight forward when only one copy of data is located in a memory, also referred to as a frame buffer. When the frame buffer is double buffered, using a frame buffer A and a frame buffer B, the process becomes more complex. This complexity occurs because the selection of either frame buffer A or frame buffer B may vary on a pixel by pixel basis when traversing the screen during a refresh. Presently, this possibility is accounted for by treating all of the data from frame buffer A and from frame buffer B. This data is sent to the DAC and any associated logic circuit needed to identify which pixels should be selected from which frame buffers for the refresh. This type of data processing requires sufficient band width to send data from both frame buffer A and frame buffer B to the DAC for presentation.
With the advent of large and inexpensive random access memory (RAM) and the increased requirements for shaded color display, the use of frame buffers has become universally accepted. A frame buffer, also often referred to as a video RAM or VRAM, is a large block of memory with two ports. One port is ‘read only’ and is used to refresh the display. The other port may be bi-directional and can be updated by a number of bits in parallel (bytes, 16 or 32 bits words are often used). Since the data rate required by the display may be very high (90 million bytes per second for a full color system), this is not a simple system and, depending on its price and technology, the maximum data rate at the port connected to the computer may have to be severely restricted.
One solution to increase the maximum data rate is to duplicate the frame-buffer memory, creating a double-buffered system in which the image in one buffer is displayed while the image in the other buffer is computed. Double-buffering allows the central processing unit (CPU) to have uninterrupted access to one of the buffers while the video controller has uninterrupted access to the other. One possible implementation provides multiplexers that connect each frame buffer to the system bus and the video controller. Double-buffering in this manner is expensive, however, since twice as much memory is needed as for a single-buffered display. Also, the multiplexers that provide dual access to the frame buffers require numerous chips, which increase the size of the system.
However, one problem with double-buffered systems is that the selection of the first frame buffer or the second frame buffer can vary on a pixel by pixel basis when traversing the screen. One method of implementing double-buffered systems involve reading the data from the first buffer, reading the data from the second buffer, and reading the data from a attribute table, and presenting all of the data to a digital to analog converter (DAC) for potential display. This approach, however, uses twice as much memory bandwidth for reading the data, and twice as many nets/pins for accessing the double data to the DAC. Therefore, it would be advantageous to have an approved method and apparatus for selecting data stored in two or more frame buffers for presentation on a display.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for a frame buffer system which includes a first frame buffer containing a first set of pixels, and a second frame buffer containing a second set of pixels. A first register is connected to an output of the first frame buffer, wherein the first register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A second register is connected to an output of the second frame buffer, wherein the second register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A selection logic is connected to the first frame buffer and to the second frame buffer. The selection logic selectively selects pixels to be read from the first frame buffer and the second frame buffer into the first register and the second register. A multiplexer has a first input connected to an output of the first register, a second input connected to an output of the second register, and an output configured for connection to a digital to analog converter. The first multiplexer selectively reads the number of pixels from the first register and the second register and a portion of the group of bytes of data for each pixel.
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Edrington Jimmie Darius
Johns Charles Ray
Voltin John Alvin
Vu Dzung Q.
Bella Matthew C.
Formby Betty
McBurney Mark E.
Monestime Mackly
Yee Duke W.
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