Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2001-12-21
2004-06-01
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S030000, C710S054000, C710S074000, C709S246000, C711S112000, C711S202000
Reexamination Certificate
active
06745266
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to format translation between systems, and more particularly, to utilization of disk cache to perform the format translations between differing systems.
BACKGROUND OF THE INVENTION
Today's computing systems have seen several decades of evolution. Evolution which has transformed one-of-a-kind, custom built machines into common, everyday appliances found in most homes today. Central processing units (CPU), which were the size of refrigerators, requiring many kilowatts (kW) of power and associated cooling, have been reduced to printed circuit board (PCB) implementations, which have proliferated the computing industry. The relatively few peripherals operated in combination with the early CPUs including tape readers, teletypes, line printers, etc., were tightly coupled to the early CPUs, which yielded highly customized computing solutions.
The integrated circuit (IC) is largely, if not wholly, responsible for the drastic reduction in the size and power requirements of the early computing solutions. In addition, the IC is largely responsible for the exponential increase in the computational capabilities of the modern day desktop computer. Through the development of the IC, not only has the CPU been reduced to printed circuit board implementations, but so have peripherals such as Random Access Memory (RAM), high resolution graphics, full motion video drivers and high bandwidth networking cards, to name only a few. Each of the peripheral applications implemented on PCB's share a common communication architecture with the CPU called the computer bus.
The computer bus allows communication between an Operating System (OS) executing on the CPU, or processor, and its peripherals. The computer bus is generally separated into several functional groups such as address, data and control. The address group of the computer bus identifies the specific peripheral attached to the computer bus as well as a particular component contained within the peripheral, such as a register or memory location. The data group of the computer bus defines the information transferred to or received from the peripheral. The control group of the computer bus defines the method or protocol used to effect data or control transfers on the computer bus. The address and control groups associated with the computer generally having a fixed number of binary units, or bits, associated with each group.
The Peripheral Component Interconnect (PCI) bus has been developed to provide coherence and standardization, improving upon the limitations of the PCI predecessors, such as Industry Standard Architecture (ISA) and the Video Electronics Standards Association Local (VL) bus. The PCI bus specification first appeared in 1992, with subsequent revisions published in 1993, 1995 and 1999. The PCI bus specification provides several features, which potentially allows PCI implementations to accommodate computer architectures for many years to come.
The PCI bus architecture facilitates peripherals, such as tape drive controllers and disk drive controllers, to be utilized by an OS executing on a CPU device. One advantage of the PCI bus is that the PCI bus allows a divergence between the PCI bus peripheral device architecture and the OS, such that the PCI peripheral device architecture has no particular correlation to the OS architecture or CPU structure.
One particular divergence between the PCI peripheral device and the OS, for example, may be the difference in minimum lengths of data records that are allowable between the OS and the PCI peripheral device. Such is the case, for example, for an OS that is operating in conjunction with a Small Computer System Interface (SCSI) hard disk that requires a minimum of one disk record, or 512 bytes for example, for each read or write operation to the SCSI hard disk. Some SCSI hard disk operations, however, only require updates to a portion of the disk record and not the entire 512-byte record.
Prior art solutions to adapt the SCSI hard disk to the OS require custom hardware channels and software drivers to match the particular SCSI hard disk access requirements to the OS in use. Data updates to the SCSI hard disk that are less than one record in length, for example, requires the prior art drivers to first read an entire record of data from the SCSI hard disk in the appropriate format. Once read, the appropriate bits within the data record are updated and finally written back to the SCSI hard disk. The prior art solution, however, departs from the essence of one of the PCI bus advantages because custom hardware and software is required of the prior art solution, in order to provide an operable interface to the SCSI PCI peripheral.
It can be seen, therefore, that there is a need for a method and apparatus to provide an operable interface between a PCI peripheral device and an OS performing Input/Output (I/O) operations using the PCI bus, without the need for custom hardware channels and software drivers.
SUMMARY OF THE INVENTION
The present invention relates to a method and apparatus for disk cache translation between a computer system and an external system.
In accordance with one embodiment of the invention, a computer system having an operating system defining the operation of the computer system that includes a first memory device containing the operating system. The operating system defines a logical interface, which includes a first queue that receives requests from the operating system, a second queue that statuses the requests received from the operating system, and a memory storage area provided for user data storage. The computer system further includes a second memory device coupled to the memory storage area to modify the user data, such that the data block size is configurable by the computer system.
In accordance with more specific embodiments of the computer system, the second memory device is operative to provide bi-directional data processing between an external device and the memory storage area and configured to optionally modify the user data received from the memory storage area through a pad translation. The second memory device is also configured to optionally modify data received from the external device through a strip translation.
In accordance with another embodiment of the invention, an article of manufacture is provided that contains a program storage medium readable by a computer. The medium tangibly embodies one or more programs of instructions executable by the computer to perform a method of operating a computer system. The method receives requests from the computer system to transfer data blocks between the computer system and an external system, allows a configurable size for the data blocks, and translates the size of the data blocks exchanged between the computer system and the external system, such that the size of the data blocks after translation align with each other.
In accordance with more specific embodiments of the method of operating the computer system, the received requests are queued in an initiation queue and managed by an I/O manager. The I/O manager statuses the received requests in a status queue. The data block size includes optionally padding the data blocks to a size compatible with a size required by the external system and optionally stripping the data blocks to a size compatible with a size required by the computer system.
In accordance with another embodiment of the invention, a method of operating a computer system is presented to receive requests from the computer system to transfer data blocks between the computer system and an external system, allowing a configurable size for the data blocks, and translating the size of the data blocks exchanged between the computer system and the external system, such that the size of the data blocks after translation align with each other.
The received requests are queued in an initiation queue and managed by an I/O manager, as well as statused by the I/O manager in a status queue. Translating the size of the data blocks received from the
Johnson Craig B.
Konrad Dennis R.
Otto Michael C.
Crawford & Maunu PLLC
Johnson Charles A.
Mai Rijue
Perveen Rehana
Starr Mark T.
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