Method and apparatus for disabling a processor core based on...

Details Method and apparatus for disabling a processor core based on... Method and apparatus for disabling a processor core based on...

2006-06-30

2009-02-17

Huisman, David J (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C714S001000, C714S047300, C718S102000

Reexamination Certificate

active

07493477

ABSTRACT:
A system includes a multi-core processor including a first processor core and a second processor core, and a core manager. The core manager is to receive data during an execution of an application by the first processor core, the data indicating a potential fault associated with the first processor core, determine to disable the first processor core based on the data, and activate the second processor core to execute the application.

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patent: 2005/0172164 (2005-08-01), Fox et al.
patent: 2006/0036889 (2006-02-01), Arai
patent: 2006/0184939 (2006-08-01), Sahoo et al.
patent: 2006/0230307 (2006-10-01), Barlow et al.

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