Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data... – Inhibiting timing generator or component
Reexamination Certificate
2005-04-19
2005-04-19
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Inhibiting timing generator or component
C713S322000
Reexamination Certificate
active
06883107
ABSTRACT:
A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.
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Rodgers Dion
Toll Bret
Wood Aimee
Blakely , Sokoloff, Taylor & Zafman LLP
Butler Dennis M.
Intel Corporation
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