Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-02-18
2002-09-17
Kim, Matthew (Department: 2186)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S028000
Reexamination Certificate
active
06453366
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for direct memory access (DMA) with dataflow blocking for users.
DESCRIPTION OF THE RELATED ART
Asynchronous Transfer Mode or ATM is a communication technology whose use is becoming more widespread in some areas while receiving competition from Gigabit Ethernet and Packet Over SONET (POS) in other areas. When the above environments are combined in a single adapter, problems result. In a communications adapter that supports a Packet over SONET physical bus called POS-PHY both cell based protocols and packet based protocols are supported. In addition to both types of protocols, multiple physicals are attached to the bus. Also multiple cell sizes are supported. In this environment, it is necessary to implement direct memory accesses (DMAs) for multiple connections to complete receive and transmit functions in a variety of operational modes.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method and apparatus for direct memory access (DMA) with dataflow blocking for users. Other important objects of the present invention are to provide such method and apparatus for direct memory access (DMA) with dataflow blocking for users substantially without negative effects and that overcome many disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.
REFERENCES:
patent: 5448714 (1995-09-01), Stodieck
patent: 5829043 (1998-10-01), Gillet et al.
patent: 5854640 (1998-12-01), North et al.
patent: 6154793 (2000-11-01), MacKenna et al.
patent: 6166748 (2000-12-01), Van Hook et al.
Broberg, III Robert Neal Carlton
Byrn Jonathan William
McBride Chad B.
McClannahan Gary Paul
International Business Machines - Corporation
Kim Matthew
Pennington Joan
Vital Pierre M.
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