Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-02-01
2004-03-16
Shin, Christopher B. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S052000
Reexamination Certificate
active
06708233
ABSTRACT:
TECHNICAL FIELD
The invention relates to serial communications and direct memory access between digital devices, including digital audio and video devices and digital computers. More particularly, the invention relates to method and apparatus for buffering header and payload data from an incoming data stream. The invention also relates to a data structure defining direct memory access descriptors for a hardware direct memory access controller.
BACKGROUND OF THE INVENTION
Digital hardware devices, such as Digital Versatile Disk (DVD) players, digital video cameras and digital audio devices are capable of generating vast amounts of digital data at high speeds. Often, such devices are used in conjunction with multimedia features of digital computers and are configured to transfer digital data on a serial bus to a host computer executing appropriate applications to render the digital data to a user.
Most state-of-the-art digital systems utilize Direct Memory Access (DMA) provided on the host computer to receive an incoming data stream directly into host memory. DMA techniques employ computer bus architectures that allow data to be sent directly to the host memory on the computer's motherboard and therefore offer the advantage of eliminating the host computer main processor's involvement in the data transfer and eliminating the additional memory bandwidth needed to move data from one buffer to another, thus speeding overall computer operation.
To foster smooth, continuous rendering of video or audio data, transfer of such data on serial buses usually occurs according to an isochronous protocol. Isochronous data transfer ensures that data flows at a pre-set rate so that applications being executed on the host computer are able to accomplish continuous rendering of audio or video images, without interruption, enhancing the user's experience of the incoming data. Isochronous data transfer typically involves the use of packets which contain a header of fixed size and payload data, which is of variable length. Header data is used for error-checking and general “housekeeping” functions, while the payload data represents the actual data, usually in a compressed or encoded format, that is to be rendered on the host computer.
Before incoming isochronous data can be decoded and utilized by a rendering application on the host computer, the payload data must be stored in a contiguous fashion in host memory. “Contiguous” as used herein means that the payload data stored in host memory represents a continuous stream of input data to a rendering application, without requiring removal of intermediate artifacts or information between the payload data corresponding to separate, consecutive packets. Thus, the header data in each packet of the incoming data stream must be separated from the respective payload data in that packet.
Conventional buffering schemes accomplish this by creating memory copies of the incoming data. Using a DMA channel, the incoming header and payload data are written directly into host memory as a large block of payload data with header data interspersed throughout. Before rendering by an application can occur, the payload data must be parsed through by an application. Parsing typically involves utilizing the main processor to copy payload data into a second buffer, discarding the header data.
Unfortunately, parsing requires main processing resources of the host computer. Moreover, this use of main processing resources is significant because of the vast amount of data that must be parsed. Since a high-speed serial bus, like the IEEE 1394 High Performance Serial Bus, is capable of data transfer speeds up to 400 Mbps (megabits per second) and therefore may transfer isochronous data into host memory at increased rates of speed, the drain on processor resources may become an obstacle to improving the user's experience of incoming digital audio and video data. It would therefore be advantageous to provide a method and apparatus for utilizing DMA to directly create a buffer of contiguous payload data from an incoming data stream, without resort to the memory copy techniques of the prior art.
SUMMARY OF THE INVENTION
The aforementioned problems are addressed by the invention, which provides a method and apparatus for directly creating a buffer of contiguous payload data from an incoming data stream. In an exemplary system, the invention provides a control program for a host controller complying with the IEEE Open Host Controller Interface 1394 Specification, Release 1.00 (OHCI 1394). The control program is implemented in the form of a novel IEEE 1394-compliant descriptor. The DMA descriptors, through appropriate software drivers, instruct the DMA engine of host controller to separate payload data and header data of each incoming packet on the isochronous stream and place it in respective buffers in host memory. Thus, two separate logical buffers may be directly created from a single incoming logical variable-length data stream.
An exemplary descriptor according to the invention includes an 8-quadlet format with respective fields for information describing the starting memory address of the header buffer and the starting memory address of the data buffer. The exemplary descriptor also includes fields representing the fixed size of the packet header data, number of bytes of header data to be stored in the header buffer, number of bytes of payload data to be stored in the payload data buffer, residual bytes left in the header buffer, residual bytes left in the payload data buffer, and a branch address to the next descriptor.
According to an exemplary process, a DMA engine configured in the host controller fetches the appropriate descriptor block when a packet in the particular DMA context arrives on the serial bus. The header data is written to the header buffer defined by the header buffer starting address and the data representing the residual header buffer size is updated. Similarly, if payload data accompanies the header, payload data is written to the data buffer defined by the data buffer starting address and the data representing the residual data buffer size is updated. If the payload data in the packet is larger than the residual data buffer size, the payload data is continued in the buffer defined by the next descriptor located at the branch address in the first descriptor.
Since the hardware controller writes the payload data in contiguous fashion, without header data, directly into the payload data buffer, the memory copy and parsing steps of the prior art are eliminated. Moreover, since header data is also written directly into the header data buffer in concatenated fashion, there is a one-to-one correspondence between the header data in the header data buffer and the payload data in the payload data buffer. This structure permits error recovery and other “housekeeping” functions to be maintained, even though the header data is stored in a separate buffer.
An additional advantage provided by an exemplary buffering scheme according to the invention permits control of the maximum amount of data (frame data in the case of digital video) stored in particular payload data buffers. By selecting a particular header buffer size, an application may provide for branching to a next DMA descriptor when the header buffer is full. Thus, if an application developer desires, for example, no more than a 50 millisecond length of frame data to be stored in each payload data buffer, the developer may specify a payload buffer size that would accommodate the maximum amount of payload data that would correspond to 50 milliseconds of frame data and specify a header buffer size that is just large enough to accommodate the number of headers that correspond to 50 milliseconds of data. The buffering scheme may be configured to branch to the next descriptor when the header buffer fills up, thus beginning a new header buffer and payload data buffer and thus controlling the maximum amount of data that can be contained in each payload data buffer.
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Chrysanthakopoulos Georgios
Fuller John Nels
Banner & Witcoff , Ltd.
Microsoft Corporation
Shin Christopher B.
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