Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-03-09
2002-07-16
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S733000
Reexamination Certificate
active
06421794
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the testing of embedded memory devices. More specifically, the present invention relates to a method and apparatus for diagnosing memory devices using self—testing circuits.
2. Background Information
Random access memory (RAM) devices are often tested by determining whether a value written to and a value later read from the same address space of the RAM match for all addresses specified within a predetermined test sequence. Various test sequences, or test algorithms, are known in the art including, for example, those defined in U.S. Pat. Nos. 4,061,908 and 5,377,148. A memory device is considered to be fault—free if, at the completion of a test, no value mismatches are found. If mismatches are found, however, additional information regarding the location and behavior of the one or more faulty cells may be desirable for several purposes. First, given the locations of the faulty cells, the RAM may be repaired by replacing the faulty cells with spare memory cells as described in U.S. Pat. No. 4,228,528. Additionally, the location and behavior of the one or more faulty cells may be mapped to physical defects to help pinpoint the cause of yield loss, as reported by S. Naik et al. in “Failure Analysis of High Density CMOS SRAMs”, published in the IEEE Design & Test of Computers, pg. 13-23, June 1993.
RAM that is incorporated inside logic circuits, as opposed to discrete stand-alone RAM, is often referred to as embedded memory. Embedded memories are more difficult to test through external means because their input and output terminals are usually directly connected to logic circuitry instead of being connected to input/output (I/O) terminals of the integrated circuit (IC). One mechanism used to facilitate embedded memory testing is known as a built-in self-test (BIST) circuit. BIST circuits are built into ICs to generate input vectors and analyze output data in response to the generated input vectors.
FIG. 1
illustrates a random access memory (RAM) device including built-in self-test (BIST) circuitry according to the prior art. Referring to
FIG. 1
, the BIST circuitry
2
is configured to test a RAM
1
containing a variable number of data blocks. During test execution, the BIST circuitry
2
generates input vectors which are input into RAM
1
through various input terminals including address input terminals
3
, data input terminals
4
, write enable terminal
5
, and chip enable terminal
6
. A bit comparator
9
is used to compare the data output
7
from the RAM
1
, with the expected data output
8
generated by the BIST circuitry
2
. A resulting initial fail vector
10
, including data indicating whether a memory failure occurred, is output by the bit comparator
9
to I/O terminals
20
. A value of “1” contained within any bit of the fail vector is referred to as a fail bit and indicates that the corresponding bit of data output does not match the expected value and therefore, may be faulty.
The bit-width, m, of the fail vector
10
is often larger than the number of output pins available on the IC. Thus, outputting the entire fail vector directly to I/O terminals, such as I/O terminals
20
, is often difficult. Conventional fail vector analyses, observe the result of a logical “OR” operation performed on the fail vector as a whole to merely detect whether any one or more bits of the data output is faulty. In order to repair faulty cells or analyze yield loss, however, the locations and behavior of the defective cells may need to be diagnosed, thereby requiring a more detailed observation of the fail vector than such conventional methods provide.
Several methodologies exist that attempt to address the problem of analyzing a large fail vector on an IC containing a relatively small number of I/O pads. First, additional I/O pads may be added to the IC to compensate for the large fail vector. This practice, however, often results in a substantial increase in circuit area and renders the IC diagnosable only before packaging. Another existing method used to analyze a large fail vector is to execute the relevant test m times (where m represents the bit-width of the fail vector), and during each test execution, one bit of the fail vector is multiplexed to the output pin. This method, however, multiplies the test duration by the bit-width of the fail vector. Another technique, disclosed in U.S. Pat. No. 5,148,398, halts test execution upon detecting a data mismatch to sequentially scan data and address information out of the chip. The interruption of test execution to scan out such information extends the time required for testing indefinitely, depending upon the number of faults encountered and the amount of data to be scanned out. Yet another technique has been reported by I. Schanstra et al. in a paper entitled “Semiconductor Manufacturing Process Monitoring Using Built-In Self-Test for Embedded Memories” published in the Proceedings of International Test Conference, Oct. 18-23, 1998. This technique recognizes faulty columns and faulty cells during testing and records their addresses and fail vectors in registers. At the end of the test, the data in the registers is serially outputted to the I/O terminals. This technique, however, is only effective at reporting the location of just a limited number of faulty cells. Furthermore, no information is provided to show whether the cell failed at reading a value of “1” or “0”, and the technique can only be used with limited test algorithms.
Thus, there is a need for a method and apparatus to diagnose failing location and behavior of RAM without significant increase in the IC area or test time.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, test data is generated and applied to an embedded memory. Actual data output from the embedded memory in response to the application of the test data is compared with expected responsive outputs to form a plurality of initial fail vectors. The initial fail vectors are compressed to form compressed fail vectors by performing a plurality of logical operations on groups of elements of a fail matrix logically formed from the initial fail vectors.
In accordance with another aspect of the present invention, a plurality of compressed fail vectors is received in which each of the plurality of compressed fail vectors comprises a plurality of representations formed in accordance with results of logical operations performed on logically grouped elements of a fail matrix which were formed from a plurality of initial fail vectors. The initial fail vectors are recovered from the compressed fail vectors by successively ascertaining values of the data elements of the fail matrix. The values are ascertained by successively examining the representations formed in accordance with the results of the logical operations and applying a plurality of determination rules specifying assignment values for the data elements of the fail matrix in accordance with at least the results of the logical operations.
In accordance with yet another aspect of the present invention, a computer system is programmed with software code to enable the computing device to receive a plurality of compressed fail vectors and to recover a plurality of initial fail vectors therefrom. The initial fail vectors are recovered by successively examining representations formed in accordance with results of logical operations performed on logically grouped elements of a fail matrix and applying a plurality of determination rules specifying assignment values for the elements of the fail matrix in accordance with at least the results of the logical operations.
In accordance with yet another aspect of the present invention, an integrated circuit comprises a comparator to logically generate a sequence of comparison outputs, a plurality of logical operation circuits, and a plurality of couplings to couple a plurality of combinations of data elements of the sequence of comparison outputs to the logical operation circuits. Such coupling enables a
Chen John T.
Rajski Janusz
Blakely , Sokoloff, Taylor & Zafman LLP
Iqbal Nadeem
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