Method and apparatus for diagnosing a LSI chip

Details Method and apparatus for diagnosing a LSI chip Method and apparatus for diagnosing a LSI chip

1986-02-03

1987-12-01

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

047109300

ABSTRACT:
Disclosed is a method of level sensitive testing of a logic array system and an LSI chip having testing means incorporated therein. The present invention is especially suitable for testing a RAM and the function of a logic unit which is a functional peripheral of the RAM. The LSI chip comprises means for selecting a specific address of the RAM, means for writing a signal at the specific address of the RAM and reading out the data from the specific address of the RAM, and means for selecting the operation of the chip between a usual operation mode and a scan-in/scan-out diagnostic mode for testing the RAM or functional peripheral of the RAM. Testing can be easily conducted by addition of a small number of logic elements. The larger the number of address signal lines and the number of data signal lines of the RAM, the more effective the testing method becomes.

REFERENCES:
patent: 4441075 (1984-04-01), McMahon
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komonytsky
patent: 4534028 (1985-08-01), Trischler
patent: 4597080 (1986-06-01), Thatte et al.

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