Partitioned scan-testing system

Details Partitioned scan-testing system Partitioned scan-testing system

1985-10-23

1987-12-01

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

047109319

ABSTRACT:
A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.

REFERENCES:
patent: 4441075 (1984-04-01), McMahon
patent: 4503386 (1985-03-01), Das Gupta et al.
patent: 4503537 (1985-03-01), McAnney
patent: 4534028 (1985-08-01), Trischler
patent: 4580137 (1986-04-01), Fiedler et al.
patent: 4597042 (1986-06-01), d'Angeac et al.
Generalized Scan Test Technique for VLSI Circuits, IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1985, pp. 1600-1604.

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