Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-04-18
2004-11-23
Thai, Xuan M. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S100000, C341S144000, C713S401000
Reexamination Certificate
active
06823416
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to an interface protocol for a device and in particular to an interface between an external controller and multiple devices arranged in a bus configuration, and is more particularly directed toward a method and apparatus for communicating between a microcontroller and a plurality of bus-compatible data conversion devices.
BACKGROUND OF THE INVENTION
Data conversion products provide the necessary bridge between analog and digital worlds. Analog-to-digital converter (ADC) products allow digital system elements, such as microprocessors and digital signal processors (DSPs) to sample analog signals, while digital-to-analog converters (DACs) permit these digital system element to generate smooth, time-varying voltages and currents. ADCs find many specific applications in modern systems, including the sampling of speech signals for telecommunications uses, while DACs are often employed to generate speech or music waveforms, to function as programmable voltage or current sources, or to precisely control analog signal levels.
For complex signal generation, it may be necessary for a single microprocessor or DSP to control multiple DACs.
FIG. 1
illustrates, in block diagram form, a data conversion device
100
of the prior art that includes multiple DACs. Although there are a number of examples of both parallel and serial interface DACs, the device
100
is designed to communicate with an external controller or processor over a serial interface.
The external controller (not shown) transmits data to the device
100
over serial data line DIN
104
, in conjunction with a serial clock signal SCLK
105
. The upper portion of the timing diagram of
FIG. 2
illustrates a typical data transmission, in which data bits transmitted from the controller on the data line DIN
104
are shifted in on low to high transitions of the serial clock SCLK
105
. It is customary in devices such as the device
100
to provide some means for addressing particular data to a specific one of the input registers
102
provided in the device
100
.
The device
100
is an example of a double-buffered device. Each of the DACs within the device
100
has an associated input register
102
and an interconnected DAC input data register
103
. If the LDAC signal
106
is held in a high logic state by the external controller, the internal DAC data registers
103
are maintained in a latched condition. That is, the data in the input registers
102
may be changed at will without affecting the DAC register
103
contents. In one mode of operation, when all DAC input registers
102
have been programmed with the desired data using the serial interface, the LDAC signal
106
is brought to a logic low level, which latches the data in the input registers
102
into the DAC data registers
103
, resulting in a simultaneous update (and corresponding output voltage changes) for all DACs in the device
100
. This is referred to as asynchronous operation, since DAC update is not tied to the operation of loading data into the input registers
102
.
It is worth noting that synchronous operation, in which data is transferred from an individual input register
102
into its associated DAC register
103
immediately upon completion of input data loading over the serial interface, is also supported. For the device
100
, this mode of operation can be selected by tying the LDAC signal
106
to a low logic state.
As will be appreciated, rapid loading of input registers
102
may be accomplished over the serial interface, followed by a simultaneous transfer of all input data into the DAC registers
103
. However, the microcontroller or DSP that is controlling the device
100
has no way of knowing how fast it may update the input register
102
data. Even if conversion of the digital input data into an analog output voltage has not been completed, the input registers
102
can still be loaded with new data, and this new data can be readily transferred into the DAC registers
103
.
At least for analog-to-digital converters, this uncertainty as to completion of data conversion has been minimized through the use of a BUSY signal.
FIG. 3
depicts, in block diagram form, an ADC
300
of the prior art that incorporates a BUSY signal.
The ADC
300
is a parallel interface device that presents eight data bits in a data bus
302
for interconnection with an associated controller (not shown), such as a microcomputer or DSP. In order to initiate a conversion of an analog input voltage
305
, the controller asserts control signal CONVST
304
, an input to the device
300
. Upon detecting the active transition of CONVST
304
, as shown in the timing diagram of
FIG. 4
, the control logic
301
of the ADC device
300
begins the data conversion process, and also asserts device output BUSY
303
by bringing the BUSY signal
303
to a logic high state.
When the BUSY signal
303
is in its logic high state, it signals to the external controller that a conversion is in progress. After the BUSY signal returns to its logic low level, the external controller may read the conversion result over the data bus
302
. Of course, the return of the BUSY signal
303
to its low logic level merely signals that data conversion has been completed. The external controller is not prevented from reading the contents of the ADC data register over the data bus
302
while BUSY is high. Of course, even though BUSY has been described as an active HIGH signal, it may just as readily be implemented as an active LOW signal. The polarity of the active transition is not a key issue; it is overall functionality that is important.
As noted, double-buffered DACs enable rapid updating of input registers combined with simultaneous data transfer (and output voltage update) for all DACs within a device. Unfortunately, in devices of the prior art, there is no way of determining precisely how rapidly the input registers of multiple DACs can be updated, since there is no indication as to whether the internal conversion operation of a particular DAC has been completed. This is particularly disadvantageous for complex systems in which multiple DAC devices (such as device
100
of
FIG. 1
) are employed. Of course, it may be possible to create empirical timing routines so that associated controllers will wait long enough for conversions to be completed before attempting DAC updates, but, in high-speed systems, there may not be code space or system time to waste on such a solution. Additional hardware resources may be required, in some cases, to perform this type of function.
Accordingly, a need arises for a device interface that permits register updates to progress as rapidly as possible without interfering with ongoing data conversions, and without the need for additional system hardware to monitor conversion status.
SUMMARY OF THE INVENTION
These needs and others are satisfied by the present invention, in which an interface is disclosed that includes a built-in indication that signal processing has been completed and that data registers in data conversion devices are ready to be re-loaded.
In short, a new system design is proposed that may use a wired-OR BUSY signal to provide maximum control and flexibility. The BUSY signal remains high while a conversion is in progress anywhere in the system. While the BUSY signal is in its high logic state, BUSY prevents any DAC data register updates from occurring. In other words, even in asynchronous modes of operation, pulsing an LDAC line low will not cause a DAC data register update until BUSY once again becomes high. This characteristic can be viewed as “stalling” (delaying) the LDAC function temporarily, or, in an alternative view, “storing” the LDAC pulse so that it becomes operative on the rising edge of the BUSY signal.
In accordance with one aspect of the invention, a method for communicating between a controller and a device with double-buffered inputs comprises the steps of providing one or more communication paths for exchanging data between the controller and the device, providing a data
Brennan Oliver James
Dempsey Dennis A.
O'Dwyer Thomas G.
Stapleton Helen
Vinereanu Tudor
Analog Devices Inc.
Thai Xuan M.
Wolf Greenfield & Sacks P.C.
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