Method and apparatus for determining the write delay time of...

Details Method and apparatus for determining the write delay time of... Method and apparatus for determining the write delay time of...

2007-03-27

2007-03-27

Cao, Chun (Department: 2115)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C711S105000, C713S401000

Reexamination Certificate

active

10761107

ABSTRACT:
A method and apparatus for determining the write delay time of a memory are provided. The apparatus includes a CPU, a memory, a north bridge chipset, a south bridge and a BIOS. The north bridge chipset, which is connected to the CPU and the memory, writes a pattern to the memory according to different write delay times. The BIOS reads the pattern stored in the memory, and checks the correctness of the read pattern to determine the common write delay time.

REFERENCES:
patent: 5047876 (1991-09-01), Genheimer et al.
patent: 6467043 (2002-10-01), LaBerge
patent: 6615345 (2003-09-01), LaBerge
patent: 6915226 (2005-07-01), Liou
patent: 385739 (1990-09-01), None

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