Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-15
2006-08-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07093217
ABSTRACT:
A method of determining an optimal transistor fanout. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that includes a dynamic resistor. The method also includes determining a steady state solution to the sizing model and determining at least one transistor fanout from the steady state solution.
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patent: 2004/0130349 (2004-07-01), Morgenshtein et al.
Rezvani et al., “LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay”, Nov. 1999, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 516-519.
Wei Chen, Cheng Ta Hsieh, Massoud Pedram, “Simultaneous Gate Sizing and Fanout Optimization”, Nov. 2000, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design.
Ivan E. Sutherland, Jon K. Lexau, “Designing Fast Asynchronous Circuits”, Mar. 2001, Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems.
Sutherland et al., Logical Effort Designing Fast CMOS Circuits, 1999.
Signore Nicholas D.
Wickman Curtis A.
Park Vaughan & Fleming LLP
Siek Vuthe
Sun Microsystems Inc.
To Tuyen
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