Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Patent
1989-02-08
1991-02-26
Simmons, David
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
156345, 204 1T, 2041292, 2041293, 20412925, 427 9, 427 10, 324439, 324444, G01N 2746
Patent
active
049959395
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a method and apparatus for determining the layer
thickness of semiconductor layer structures, i.e., the layer thickness of each layer of a multilayer semiconductor structure, primarily of hetero transitions.
When III-V type semiconductors are used for opto electronic applications or in the field of microelectronics when such semiconductors are used as fast operating switching elements, layer structures are widely used which consist of thin layers of differing materials wherein the layer thickness may vary between 5 nm and 1-2 .mu.m. In case of so-called super grid structures the number of layers can be as high as 60-100. When electron microscope is used for the examination or determination of such a high number of layers with such a small thickness, the accuracy will not be sufficiently high and the determination will be limited to the location of the metallurgic transition and it will not be effective for measuring the physical transition. Conventional C-V measurements using a metal contact cannot provide sufficient accuracy either, because owing to the typically high (10.sup.17 atoms/cm.sup.3) concentration of charge carries the depth of the attainable depletion zone is below 1 .mu.m and the layer structure which should be examined can have a thickness of several times 10 .mu.m.
The most advanced known technique for the determination of the layer thickness utilizes profile-measurement methods based on C-V measurements of electrolyte-semiconductor transitions. Such a method is disclosed in the papers of M. M. Faktor, T. Ambridge, C. R. Elliott and J. C. Regnault: `The Characterization of Semiconductor Materials and Structures Using Electrochemical Techniques` (Current Topics in Materials Science, Vol. 6 1980, Ed: E. Kaldis, North-Holland, Amsterdam), as well as in the paper of P. Blood: `Capacitance-Voltage profiling and the Characterization of III-V Semiconductors Using Electrolyte Barrier` (Semicond. Sci. Technol. 1, pp. 7-17, 1986).
In this method an electrolyte was used which, on the one hand was capable of ensuring that a depletion zone be established between the electrolyte and the semiconductor with a suitable bias and on the other hand was able to ensure that the electrolyte can penetrate till any required depth in the examined sample by means of anodic etching. The depletion zone was established by using a typically 1 V reverse bias, the capacitance of the sample was measured by means of a modulating signal having a typical frequency of 3 kHz derived by a frequency of about 30 Hz and this value was used for the determination of the concentration of the examined semiconductor sample. If the current flowing through the electrolyte is integrated, then the depth of penetration of the etching front can be determined by using Faraday's law.
This method provides good results when thicker layers are examined, in case of thinner layers, however, very small etching currents should be adjusted, therefore the etching process goes on in very small steps, i.e. steps of 1 nm only, because otherwise an integrated layer would be obtained instead of the layers to be examined (see FIG. 23 of the above referred publication of `Blood`). From these limitations it follows that the examination requires long time and the results of the measurements can be dependent from fluctuations of the temperature, and for the determination of the actual location of the transition from the results of the measurements only approximative calculations exist which have errors as high as the layer-thickness.
It is known from the literature of the pertinent art that in the presence of deep levels the realistic member of the admittance follows the high frequency measuring signal with a phase-delay, if the frequency of the measuring signal is higher than the time constant of the thermic emission of the deep levels. This fact is supported by references, e.g. in the publication of D. L. Losee: `Admittance Spectroscopy of Impurity Levels in Schottky Barriers` (J. Appl. Phys. 46. pp. 2204-2214, 1975).
It is also a known
REFERENCES:
patent: 3874959 (1975-04-01), Hoekstra et al.
patent: 3902979 (1975-09-01), Thomas
patent: 4028207 (1977-06-01), Faktor et al.
patent: 4310389 (1982-01-01), Harbulak
patent: 4487661 (1984-12-01), Barraud et al.
Characterization of Semiconductor Materials and Structures . . . (Current Topics in Materials Science, vol. 6, 1980), M. M. Factor et al.
Capacitance-Voltage Profiling and the Characterisation of III-V Semiconductors . . . (Semicond. Sci. Technol. 1, pp. 7-27, 1986), P. Blood.
Admittance Spectroscopy of Impurity Levels in Shottky Barriers (J. Appl. Phys. 46, pp. 2204-2214, 1975), D. L. Losee.
Aszodi Gabor
Boda Janos
Erdelyi Katalin
Ferenczi Gyorgy
Fule Gyorgy
Dang Thi
Magyar Tudomanyos Akademia Muszaki Fizikai Kutato Intezete
Simmons David
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