Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-12-17
2000-03-07
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711154, 711156, 711169, 711172, 711163, 709214, G06F 1300
Patent
active
060353775
ABSTRACT:
A method implemented in hardware to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Each processing node further includes page access counter search logic connected to the plurality of page access counters, which is enabled upon completion of page access monitoring, for sequentially comparing the contents of each page access counter with a predetermined minimum count value to identify the page access counters having contents equal to or greater than the minimum count value, and to identify the memory page addresses associated with the page access counters having contents equal to or greater than the minimum count value. This information can thereafter be used to optimize memory and process assignments in the computer system.
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James Larry C.
Stonecypher, Jr. Thomas E.
Bataille Pierre Michel
Cabeca John W.
NCR Corporation
Stover James M.
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