Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-06-24
2000-02-15
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711148, 711153, 711208, 709213, 709216, G06F 1200
Patent
active
060264721
ABSTRACT:
A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.
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Cochcroft, Jr. Arthur F.
James Larry C.
McDonald Edward A.
Washington Peter
Bataille Pierre-Michel
Cabeca John W.
Intel Corporation
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