Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-07-31
2001-08-07
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S157000, C711S168000, C711S005000
Reexamination Certificate
active
06272594
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer memory systems. More specifically, the present invention relates to routing address signals to memory banks in a computer system to achieve various memory interleaving strategies.
DESCRIPTION OF THE RELATED ART
In the art of computing, it is common to store program instructions and data in dynamic random access memory (DRAM). The most common type of DRAM memory cell is a single transistor coupled to a small capacitor. A data bit is represented in the memory cell by the presence or absence of charge on the capacitor. The cells are organized into an array of rows and columns.
FIG. 1
is a block diagram of a typical prior art memory chip
10
that is based on a 4 megabit memory array
12
having 2,048 rows and 2,048 columns. Memory chip
10
has a 4 bit wide data input/output path. Row demultiplexer
15
receives an 11 bit row address and generates row select signals that are provided to memory array
12
. Page buffer
14
acts as a temporary storage buffer for rows of data from array
12
. Column multiplexer
16
receives a 9 bit column address and multiplexes the 4 bit data input/output path to a selected portion of buffer
14
.
The distinction between rows and columns is significant because of the way a memory access proceeds. Page buffer
14
is formed from a single row of cells. The cells act as a temporary staging area for both reads and writes. A typical DRAM access consists of a row access cycle, one or more column accesses cycles, and a precharge cycle. The precharge cycle will be described in greater detail below.
The row access cycle (also called a page opening) is performed by presenting the row address bits to row demultiplexer
15
to select a row. The entire contents of that row are then transferred into page buffer
14
. This transfer is done in parallel, and it empties all memory cells in that row of their contents. The transfer is done by driving whatever charge exists in each row capacitor down to a set of amplifiers that load page buffer
14
. This operation also erases the contents of the capacitors of the row that is accessed. For typical prior art DRAMs, this operation takes approximately 30 ns.
Next, the column access cycle is performed by presenting the column address bits to select a particular column or set of columns, and the data is either read from or written to page buffer
14
. During the column access cycle, page buffer
14
acts as a small RAM. The typical access delay for this operation is approximately 30 ns to receive the first 4 bits of data, and 10 ns to receive subsequent 4 bit chunks of data. Several consecutive accesses can be made to the page to access different columns, thereby allowing the entire row to be written to or read from very quickly. For a typical four bit wide DRAM such as that shown in
FIG. 1
, a page of 2,048 bits (or 256 bytes) can be read out in 512 accesses, or 5.14 &mgr;s. Accordingly, the bandwidth of DRAM chip
10
is 49.8 megabytes per second. It is easy to see how a few DRAM chips in parallel can yield very high bandwidth.
The final cycle of the memory access is the precharge cycle, which is also known in the art as page closing. As discussed above, the row access cycle destroyed the contents of the capacitors of the row that was read into buffer
14
. Before another row can be read into buffer
14
, the contents in page buffer
14
must be transferred back to memory array
12
. This process is called the precharge cycle. In most prior art DRAM chips, no address is required because the address of the open row is latched when the contents of that row are transferred into buffer
14
, and that address is retained as long as the page is open. Typically, the precharge cycle lasts about 40 ns.
In addition to the normal read and write access cycles, most DRAMs also require refresh cycles. The small capacitors that make up each memory cell suffer from leakage, and after a short period of time, the charge will drain away. To prevent the loss of data, each row must be precharged (opened and closed) at a certain minimum rate. The size of the capacitors and leakage allowed is balanced with the size of the array in such a way that the number of refresh cycles required is a small fraction of the total bandwidth of the DRAM. Typically, DRAMs are engineered such that refreshing the rows at a rate of one row per 15.6 microseconds is sufficient to maintain the data. Accordingly, while data can be written to and read from page buffer
14
many consecutive times, buffer
14
cannot be held open indefinitely because it must be periodically closed to allow other rows to be refreshed.
There are two primary types of DRAMs known in the art, asynchronous DRAMs and synchronous DRAMs. Asynchronous DRAMs do not have a clock input. Rather, complex timing constraints among various signals and addresses must be satisfied in order for the DRAM to operate properly. The two main control pins for asynchronous DRAMs are “row address strobe” (RAS) and “column address strobe” (CAS). To open a row, RAS is asserted (typically, lowered). To close a row, RAS is deasserted. To access a column CAS is asserted, and to access another column, CAS must be deasserted and then reasserted. Note that CAS can be asserted and deasserted multiple times while RAS is asserted.
In contrast to asynchronous DRAMs, synchronous DRAMs (SDRAMs) accept a clock input, and almost all timing delays are specified with respect to this clock. In addition, SDRAMs usually have between two and eight different logical arrays of memory (or banks) that can operate independently. Rather than use separate RAS and CAS signals for each bank, a sequence of commands is sent to the DRAM synchronously to perform page opening, column access, and page closing functions. Additional address bits are used for bank selection. One major benefit provided by SDRAMs is pipelining. While one bank is being accessed, another bank can be refreshed or precharged in the background.
Despite these differences, SDRAM organization is very similar to asynchronous DRAM organization. In fact, many memory controllers for asynchronous DRAMs support multiple banks and background refreshing and precharging operations.
In the prior art, the term “bank” was traditionally used to denote a group of asynchronous DRAM chips that where accessed in parallel. Accordingly, a bank was accessed by generating a bank select signal, along with appropriate row and column addresses, as described above. However, a single SDRAM chip has multiple banks. Therefore, the term “rank” is used to denote a group of SDRAM chips that are accessed in parallel, and additional bank bits are routed to the SDRAM rank. In a system capable of supporting either SDRAMs or asynchronous DRAMs, typically the higher order bank bits that are used when accessing asynchronous DRAMs are used as rank bits when accessing SDRAMs, and the lower order bank bits that are used when accessing asynchronous DRAMs are routed to the SDRAMs. It should be noted that each bank within an SDRAM rank has its own set of page buffers.
DRAM chips can be organized to form main memory systems in a variety of ways. Typically the width and speed of the system bus are synchronized to the width and speed of the main memory system bus by providing the main memory system bus with the same bandwidth as the system bus. Usually system busses are both faster and wider than the data I/O interface provided by individual DRAM chips, so multiple DRAM chips are arranged in parallel to match the bandwidth of the system bus. If a particular computer system has a 16 byte wide data bus that operates at 66 MHZ, then a main memory subsystem of the computer system that operates at 33 MHZ and is constructed with 4-bit wide DRAM chips will typically have 64 DRAM chips arranged in each bank, thereby providing each bank with a bandwidth of nearly a gigabyte per second, which matches the bandwidth of the system data bus. If the bandwidths are not matched, other techniques may be employed, such as using a small FIFO to buffer memory accesses and blocking
Gupta Anurag
Kabil Amil
Anderson Matthew D.
Hewlett--Packard Company
Kim Matthew
Plettner David A.
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