Method and apparatus for determining chip arrangement...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07346886

ABSTRACT:
In determining a relative position between a chip lattice including rectangular cells, each of which has a size of a chip to be formed on a substrate and an effective area on the substrate, one representative cell in the chip lattice is divided into a plurality of partial areas in accordance with an existing area, of a representative point of the effective area, in which chip sets trimmed from the chip lattice with the effective area are identical. A partial area corresponding to a chip set including a maximum number of chips is specified from the plurality of partial areas, and the representative point is set in the specified partial area.

REFERENCES:
patent: 6314548 (2001-11-01), Suzuki
patent: 63-250811 (1988-10-01), None
patent: 7-211622 (1995-08-01), None
patent: 11-274053 (1999-10-01), None
patent: 2000-195824 (2000-07-01), None
patent: 2003-257843 (2003-09-01), None

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