Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2009-05-22
2011-11-22
Phan, Trong (Department: 2827)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S120000, C711S121000, C711S122000, C711S128000, C711S129000, C711S137000, C711S204000, C711S205000
Reexamination Certificate
active
08065485
ABSTRACT:
A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.
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Caprioli Paul
Levinsky Gideon N.
Yip Sherman H.
Heter Erik A.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Oracle America Inc.
Phan Trong
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