Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-11-06
2007-11-06
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
10448826
ABSTRACT:
A method and apparatus for facilitating the determination of a status of an asynchronous memory (e.g., how full or empty the memory is). A write pointer to the memory is maintained in a first clock domain; a read pointer is maintained in a second clock domain. The pointers are maintained in a non-binary code format promoting minimum bit transitions as the pointers increment (e.g., Gray code). Each pointer is transmitted to the other clock domain through synchronizers. Each synchronizer comprises multiple sets of D flip-flops. In each clock domain, the write pointer and read pointer values are converted to mathematically useful formats (e.g., binary), and their difference is calculated. The difference indicates how much space in the memory is or is not used, and may be compared to a non-zero threshold.
REFERENCES:
patent: 5426756 (1995-06-01), Shyi et al.
patent: 6263410 (2001-07-01), Kao et al.
patent: 6389490 (2002-05-01), Camilleri et al.
Nguyen Hiep T.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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