Method and apparatus for determining a process model that...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07546558

ABSTRACT:
One embodiment can provide a system for determining a process model that models an effect of one or more semiconductor manufacturing processes. During operation, the system can receive a test layout. Next, the system can receive empirical data which is obtained using a process that includes subjecting the test layout to one or more semiconductor manufacturing processes. The system can then receive a set of functions which includes a feature-detecting function, wherein the feature-detecting function's value at an evaluation point is associated with the presence of a particular shape in proximity to the evaluation point. Next, the system can determine the process model using the test layout, the empirical data, and the set of functions.

REFERENCES:
patent: 5991006 (1999-11-01), Tsudaka
patent: 6289499 (2001-09-01), Rieger et al.
patent: 7053355 (2006-05-01), Ye et al.
patent: 2005/0268256 (2005-12-01), Tsai et al.
patent: 2005/0278060 (2005-12-01), Furuya
patent: 2008/0104555 (2008-05-01), DeMaris et al.

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