Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-06-14
2004-09-21
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S212000, C365S049130, C365S203000
Reexamination Certificate
active
06795892
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to content addressable memories (CAMs), and more particularly to intra-row configurability of a CAM array.
BACKGROUND
A content addressable memory (CAM) system is a storage system that can be instructed to compare a specific pattern of comparand data with data stored in its associative CAM array. The entire CAM array, or segments thereof, is searched in parallel for a match with the comparand data. The CAM device typically includes a priority encoder to translate the highest priority matching location into a match address or CAM index.
The CAM array has rows of CAM cells that each store a number of bits of a data word. U.S. Pat. No. 5,440,715 describes a technique for expanding the width of the data words beyond that of a single row of CAM cells. This inter-row configurability provides flexibility in the use of the single CAM array to store data words larger than that available in a single addressable row of CAM cells.
It would be desirable to have a CAM system that includes intra-row configurability to provide additional flexibility in the use of a single CAM array to be used in multiple array configurations. Intra-row configurability is the ability to access and operate upon one or more segments of rows of CAM cells.
SUMMARY OF THE INVENTION
A method and apparatus for determining a match address in an intra-row configurable CAM system is disclosed. For one embodiment, the CAM system includes a CAM array and priority encoding circuitry. The CAM system includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The priority encoding circuitry is coupled to the match line segments and has inputs to receive configuration information indicative of a width and depth configuration of the CAM array. The priority encoding circuitry is configured to generate a first match address in the CAM array corresponding to a row segment that stores data matching first comparand data in response to first configuration information, and is further configured to generate a second match address in the CAM array corresponding to a group of row segments that store data matching second comparand data in response to the second configuration information. The first and second configuration information correspond to different width and depth configurations.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Ken Schultz and Andrew Sorowka, “High Performance CAMs for 10GB/s and Beyond”, Gigabit Ethernet Conference (GEC2000), Mar. 27, 2000, pp. 147-154.
Pereira Jose Pio
Srinivasan Varadarajan
Bataille Pierre
Netlogic Microsystems Inc.
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