Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-03-28
2006-03-28
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S154000, C711S167000
Reexamination Certificate
active
07020762
ABSTRACT:
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.
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International Search Report for International Application No. PCT/US03/38727 Mailed Aug. 19, 2004.
Rohillah Anwar Q.
Sprangle Eric A.
Fagan Matthew C.
Intel Corporation
Padmanabhan Mano
Patel Kaushik
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