Method and apparatus for detection and isolation during...

Details Method and apparatus for detection and isolation during... Method and apparatus for detection and isolation during...

2006-05-23

2006-05-23

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07051303

ABSTRACT:
A method for providing verification for a simulation design involves analyzing a simulation design using a testbench comprising a rapid bug detection tool, and if a bug is detected, adding a bug isolation tool to the testbench, and isolating and eliminating the bug using the testbench comprising the bug isolation tool.

REFERENCES:
patent: 6493852 (2002-12-01), Narain et al.
patent: 6539523 (2003-03-01), Narain et al.
patent: 6591403 (2003-07-01), Bass et al.
patent: 6678875 (2004-01-01), Pajak et al.
patent: 6785873 (2004-08-01), Tseng
patent: 2004/0015739 (2004-01-01), Heinkel et al.

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