Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Patent
1998-01-30
2000-10-17
Sheikh, Ayaz R.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
714 53, 714758, G06F 1100
Patent
active
061346993
ABSTRACT:
A method and apparatus are provided for detecting virtual address parity error for a translation lookaside buffer in a computer system. The computer system includes a processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a translation lookaside buffer (TLB) and a segment lookaside buffer (SLB). A virtual address parity (VAP) is generated for each entry written in the segment lookaside buffer (SLB). A virtual address parity (VAP) is generated for each virtual address entry written in the translation lookaside buffer (TLB). The SLB virtual address parity (VAP) and the TLB virtual address parity (VAP) are utilized for identifying a translation miss condition.
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Steenburgh James Anthony
Woodward Sandra S.
Davis, II William L.
International Business Machines - Corporation
Pennington Joan
Sheikh Ayaz R.
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