Method and apparatus for detecting soft errors in content addres

Details Method and apparatus for detecting soft errors in content addres Method and apparatus for detecting soft errors in content addres

1997-12-05

2000-05-23

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714758, 714800, G06F 1110

Patent

active

060676566

ABSTRACT:
The invention comprises, in one aspect, a content addressable memory array having a plurality of memory locations to store tag words. The content addressable memory array includes a parity encoder and a parity comparator. The parity encoder has a first input terminal to receive an input data signal and a first output terminal to deliver a signal representative of the parity of the input data signal. The parity comparator has a second input terminal, a third input terminal connected to the first output terminal, and a plurality of memory cells to store original parities of the tag words. The parity comparator compares the original parity of a first tag word to the parity of the input data signal in response to a receiving a match signal. The content addressable memory array includes a fourth input terminal to receive the input data signal, and a second output terminal to send the match signal in response to one of the tag words matching the input data signal. The second output terminal connects to the second input terminal.

REFERENCES:
patent: 3997882 (1976-12-01), Goyal
patent: 5428565 (1995-06-01), Shaw
patent: 5491703 (1996-02-01), Barnaby et al.
patent: 5752260 (1998-05-01), Liu
patent: 5796758 (1998-08-01), Levitan

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