Method and apparatus for detecting phase or frequency lock

Details Method and apparatus for detecting phase or frequency lock Method and apparatus for detecting phase or frequency lock

1994-08-08

1996-01-09

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 331 1A, 331DIG2, H03D 324

Patent

active

054835585

ABSTRACT:
A lock detection circuit (112) includes a first sampler (113) which samples an input signal (102) at a rate of an output signal (109) to provide a sampled input signal. A second sampler (114) which samples a feedback signal (111) at the rate of the output signal (109) to provide a sampled feedback signal. The sampled input signal is subsequently sampled by a third sampler (115) at the rate of the feedback signal. The sampled feedback signal is subsequently sampled by a fourth sampler (116) at the rate of the input signal. The second sampled input signal and the second sampled feedback signal are subsequently compared (117) and when they substantially match, an indication (122) is set to indicate that phase and/or frequency lock has been obtained.

REFERENCES:
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5166644 (1992-11-01), Saito et al.

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