Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Patent
1997-09-11
2000-05-30
Donaghue, Larry D.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
712218, 712 23, 712225, G06F 1128
Patent
active
060702389
ABSTRACT:
One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.
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Feiste Kurt Alan
Muhich John Stephen
White Steven Wayne
Donaghue Larry D.
England Anthony V. S.
International Business Machines - Corporation
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