Method and apparatus for detecting multiple matches in a content

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365 49, 36518908, 364DIG1, 39542106, 39542107, G06F 1300, G11C 1500, G11C 1504

Patent

active

054540941

ABSTRACT:
A circuit and method for detecting multiple matches or hits in a content addressable memory (CAM) are disclosed. The circuit includes a logarithmic index generator or encoder, and a converter which provides a unary signal to an attached random access memory (RAM) in order to protect the RAM from simultaneous multiple addressing attempts. The circuit also includes a plurality of inverters for inverting the unary signal, and generates a signal indicating the presence of multiple matches in the content addressable memory when corresponding digits of the inverted unary signal and an address signal are both asserted. The circuitry for generating the multiple match signal includes a plurality of AND gates coupled to output lines of the CAM, a plurality of line transistors, and a pull-up transistor coupled to a multiple match or hit line.

REFERENCES:
patent: 3800286 (1974-03-01), Brown et al.
patent: 4670858 (1987-06-01), Almy
patent: 4831586 (1989-05-01), Nakagawa et al.
patent: 4928260 (1990-05-01), Chuang et al.
patent: 5329405 (1994-07-01), Hou et al.

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