FET having a high trap concentration interface layer

Details FET having a high trap concentration interface layer FET having a high trap concentration interface layer

1989-08-28

1991-01-22

Mintel, William

357 15, 357 16, 357 63, H01L 2980

Patent

active

049874632

ABSTRACT:
A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

REFERENCES:
patent: 4688062 (1987-08-01), Liles
patent: 4745448 (1988-05-01), Van Rees et al.
Horio et al., "Numerical Simulation of GaAs MESFET's on the Semi-Insulating Substrate Compensated by Deep Traps", IEEE Transactions on Electron Devices, vol. 35, No. 11, Nov. 88, 1778-1785.
Paulson et al., "The Effects of Implanted Oxygen on the Backgating Characteristics of GaAs IC's".
Smith et al., "Sidegating Reduction for GaAs Integrated Circuits by Using a New Buffer Layer".
Mishra et al., "Impact of Buffer Layer Design on the Performance of AlInAs-GaInAs HEMTs," IEEE 47th Annual Device Research Conference, Jun. 19-21, '89, Cambridge, MA, p. IVB-3.
Melloch et al., "Effect of a GaAs Buffer Layer Grown at Low Substrate Temperatures on a High-Electron-Mobility Modulation-Doped Two-Dimensional Electron Gas," Appl. Phys. Lett., 54 (10), Mar. 6, 1989, pp. 943-945.
Smith et al., "New MBE Buffer Used to Eliminate Backgating in GaAs MESFETs," IEEE Electron Device Letters, vol. 9, No. 2, Feb. '88, pp. 77-80.

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