Method and apparatus for detecting low pin count and serial...

Details Method and apparatus for detecting low pin count and serial... Method and apparatus for detecting low pin count and serial...

2006-02-14

2006-02-14

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S105000

Reexamination Certificate

active

07000056

ABSTRACT:
Apparatus and method for providing a multiplexed bus supporting the coupling of either one of a device having a first bus type interface and a device having a second bus type interface where the multiplexed bus is made up, at least in part, of a plurality of common signal lines that may be coupled to either type of device, and that may be used to carry out transfers with protocols and timings for either bus.

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“A comparison of five different multiprocessor SoC bus architectures” by Kyeong Keol Ryu; Eung shin; Moomey, , V.J. (abstract only) Publication Date Sep. 4-6, 2001.
U.S. Appl. No. 08/581,378: A Method and Apparatus for Automatically Detecting Whether a Memory Unit Location is Unpopulated or Populated with Synchronous or Asynchronous Memory. Specification and abstract pp. 2-34. Figures 1, 2, 3A and 3B. Inventors: Narenda S. Khandekar and Aniruddha Kundu.
PCT International Search Report, International application No. PCT/US2004/004220, Jan. 12, 2005, 4 pages.

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