Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2007-08-21
2007-08-21
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000
Reexamination Certificate
active
10718282
ABSTRACT:
A device and method to detect and correct for clock duty cycle skew in a high performance microprocessor having a very high frequency clock. The device includes a delay chain circuit to delay the clock signal and to determine the presence of clock duty cycle skew. The device uses simple latches, flops, and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of a more uniform time duration.
REFERENCES:
patent: 5491440 (1996-02-01), Uehara et al.
patent: 6181178 (2001-01-01), Choi
patent: 6326827 (2001-12-01), Cretti et al.
patent: 6384652 (2002-05-01), Shu
patent: 6489819 (2002-12-01), Kono et al.
patent: 6578154 (2003-06-01), Wynen et al.
patent: 6687844 (2004-02-01), Zhang
Perveen Rehana
Schwegman Lundberg Woessner & Kluth P.A.
Yanchus, III Paul
LandOfFree
Method and apparatus for detecting and correcting clock duty... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for detecting and correcting clock duty..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for detecting and correcting clock duty... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3888319