Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-12-26
2002-06-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C714S811000
Reexamination Certificate
active
06412052
ABSTRACT:
TECHNICAL FIELD
The present invention relates to packetized dynamic random access memory devices, and more particularly, to a method in apparatus for detecting a signal indicating the start of an initialization procedure that adjusts the timing of an internal clock signal used to strobe the initialization signal and a command packet.
BACKGROUND OF THE INVENTION
Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of the computer system, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 200 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 200 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as “SyncLink.” In the SyncLink architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of a computer system
10
using the SyncLink architecture is shown in FIG.
1
. The computer system
10
includes a processor
12
having a processor bus
14
coupled to three packetized dynamic random access memory or SyncLink DRAM (“SLDRAM”) devices
16
a-c
through a memory controller
18
. The computer system
10
also includes one or more input devices
20
, such as a keypad or a mouse, coupled to the processor
12
through the processor bus
14
, a bus bridge
22
, and an expansion bus
24
, such as an Industry Standard Architecture (“ISA”) bus or a Peripheral Component Interconnect (“PCI”) bus. The input devices
20
allow an operator or an electronic device to input data to the computer system
10
. One or more output devices
30
are coupled to the processor
12
to display or otherwise output data generated by the processor
12
. The output devices
30
are coupled to the processor
12
through the expansion bus
24
, bus bridge
22
and processor bus
14
. Examples of output devices
24
include printers and a video display units. One or more data storage devices
38
are coupled to the processor
12
through the processor bus
14
, bus bridge
22
, and expansion bus
24
to store data in or retrieve data from storage media (not shown). Examples of storage devices
38
and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.
In operation, the processor
12
communicates with the memory devices
16
a-c
via the memory controller
18
. The memory controller
18
sends the memory devices
16
a-c
command packets that contain both control and address information. Data is coupled between the processor
12
and the memory devices
16
a-c
through the memory controller
18
and the processor bus
14
. Although all the memory devices
16
a-c
are coupled to the same conductors of the memory controller
18
, only one memory device
16
a-c
at a time reads or writes data, thus avoiding bus contention. Bus contention is avoided by each of the memory devices
16
a-c
having a unique identifier, and the command packet containing an identifying code that selects only one of these components.
The computer system
10
also includes a number of other components and signal lines that have been omitted from
FIG. 1
in the interests of brevity. For example, as explained below, the memory devices
16
a-c
also receive a command clock signal to provide internal timing signals, a data clock signal clocking data into the memory device
16
, and a FLAG signal signifying the start of a command packet.
One of the memory devices
16
a
is shown in block diagram form in FIG.
2
. The memory device
16
a
includes a clock generator circuit
40
that receives a command clock signal CMDCLK and generates an internal clock signal ICLK and a large number of other clock and timing signals to control the timing of various operations in the memory device
16
. The memory device
16
also includes a command buffer
46
and an address capture circuit
48
, which receive the internal clock signal ICLK, a command packet CA
0
-CA
9
on a 10-bit command bus
50
, and a FLAG signal on line
52
. The memory controller (not shown) or other device normally transmits the command packet CA
0
-CA
9
to the memory device
16
a
in synchronism with the command clock signal CMDCLK. As explained above, the command packet, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence, as described in greater detail be
Keeth Brent
Manning Troy A.
Chace Christian P.
Dorsey & Whitney LLP
Kim Matthew
Micro)n Technology, Inc.
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