Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-28
2002-09-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06446246
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of computer-aided design and, more particularly, to routing for integrated circuit designs.
2. Discussion of Related Art
The physical design process for most integrated circuit chips typically includes floorplanning, global routing and detail routing processes, each of which may be performed multiple times. During floorplanning, functional unit or other types of blocks may be placed within a model of the chip. The floorplanning process is followed by a global routing process during which nets or wires between the blocks and their corresponding terminals are placed within the model for purposes of timing and other cost estimations and to roughly estimate their final placement in the integrated circuit layout. Detail routing follows global routing and determines the actual placement of wires between and within integrated circuit blocks in the layout and associated terminals and vias.
Most currently available detail routers typically fall into one of two categories: design rule-correct routers or design-rule incorrect routers. Design rule-correct routers only route a wire if it can be done without violating any design rules. Where such a router determines that a wire cannot be routed without violating a design rule, the router will not complete the routing process. In contrast, design rule-incorrect routers typically complete the routing process, but may create new design rule violations in so doing. Where a wire cannot be routed without creating a new design rule violation, the design-rule incorrect router will route the wire, but may do so in an undesirable manner.
Referring to
FIG. 1
, in a typical very large scale integration (VLSI) design process, designers specify obstacles
115
, also referred to as keep out regions or KORs, along with terminals
105
,
106
,
107
and nets. For a conventional routing process, design rules specify that wires (and other layout objects) should be separated from obstacles by a specified distance that may be particular to the obstacle and/or object. The obstacles may include anything from a small discrete object to a functional block, for example, but may be any area that the designer wants to be avoided during a particular detail routing pass. An issue may arise when a wire is to be routed to a terminal
105
,
106
or
107
that overlaps with the obstacle
115
or that is less than the specified distance from an obstacle.
A design rule-correct router may not route the wire because there may be no way to do so while maintaining the specified distance between the wire and the obstacle. A design rule-incorrect router will route the wires even if a new design rule violation (DRV) is created in the process as shown in FIG.
2
.
For this example, regardless of the type of router used, additional post-processing may be involved. This post-processing may include, for example, manual routing of the wire, reviewing the routing in violation, and possibly re-routing the wire to ensure that issues such as notching and exfoliation, for example, are avoided. With the density and complexity of typical VLSI designs, such issues may arise frequently causing this post-processing step to be time consuming.
A somewhat similar issue may arise when routing a multi-terminal net as illustrated in FIG.
3
. For example, a first wire
305
in a multi-terminal net has been routed between two terminals of the net. A second wire of the multi-terminal net is to be routed from a next terminal T
1
to a specified terminal T
2
on the first wire
305
. If the first wire
305
is not considered to be an obstacle, the router may choose any route to the terminal T
2
without observing any design rule spacings with respect to the wire
305
.
If on, the other hand, the first wire
305
is considered an obstacle when the second wire is being routed, a design rule correct router will not complete the routing pass. A design rule-incorrect router will introduce a new design rule violation when connecting the second wire to the first wire because the second wire cannot be connected to the specified terminal T
2
without violating design rule spacings with respect to the first wire
305
. The routing causing the design rule violation may be acceptable, or, as shown in
FIG. 4
, it may be problematic.
Whenever a new design rule is introduced, additional processing, whether manual or automatic, may be involved as mentioned above. Such additional processing adds time and expense to the design process. Thus, it is desirable to avoid introducing new design rule violations whenever possible.
SUMMARY OF THE INVENTION
A method and apparatus for detail routing using obstacle carving around terminals are described.
In accordance with one embodiment, a method includes identifying a terminal in an integrated circuit layout object that is separated from an obstacle by less than a design rule spacing, and carving the obstacle to reduce an area of the obstacle by an overlap between the obstacle and the terminal bloated by the spacing.
Other features and advantages of the present invention will be appreciated from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5847968 (1998-12-01), Miura
Do Thuan
Faatz Cynthia T.
Smith Matthew
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