Method and apparatus for deskewing clock signals

Details Method and apparatus for deskewing clock signals Method and apparatus for deskewing clock signals

1997-10-07

2000-06-13

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375371, 395552, 327152, 327149, H03D 324

Patent

active

060758325

ABSTRACT:
An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.

REFERENCES:
patent: 4789996 (1988-12-01), Butcher
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5398262 (1995-03-01), Ahuja
patent: 5675273 (1997-10-01), Masleid
patent: 5819076 (1998-10-01), Jeddeloh et al.
PCT Search Report for International Application No. PCT/US98/17399, mailed Jan. 27, 1999, 5 pages.

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