Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-05-26
2002-01-01
Everhart, Caridad (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06336207
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to technology for designing an LSI layout. More particularly, the present invention relates to LSI layout designing technology, in which cells are interchanged in such a manner as to satisfy required specifications about timing, power consumption and the like.
FIG. 16
is a flow chart illustrating the processing procedure of a conventional LSI layout designing method in accordance with standard cell processing.
In input processing S
51
, required specifications
51
about timing, power consumption and the like, circuit designing information
52
obtained by logical designing and a cell library
53
are input.
FIG. 17
is a schematic representation diagrammatically illustrating the cell library
53
for use in conventional LSI layout designing. In the cell library
53
, a plurality of cells having such logic functions as required for operating an LSI are provided. Among these cells, there are some cells having equivalent logic but different transistor sizes, i.e., different levels of drivability (e.g., output current and output voltage).
In conventional standard cell processing in general, a restriction is imposed on cells that the cells have an equal height. On the other hand, no restriction is imposed on the widths of the cells, which may be set at arbitrary values. Accordingly, when there are cells having equivalent logic and mutually different levels of drivability, a cell having a larger level of drivability tends to be designed to have a larger cell width.
In
FIG. 17
, cells
61
A,
61
B and
61
C are logically equivalent cells (implemented as inverters), the levels of drivability of which increase in the order of
61
A<
61
B<
61
C. More specifically, the cells
61
A,
61
B and
61
C have an equal height but mutually different widths, which increase in the order of
61
A<
61
B<
61
C. Similarly, cells
62
A,
62
B, and
62
C are logically equivalent cells (implemented as two-input AND gates), the levels of drivability of which increase in the order of
62
A<
62
B<
62
C. Similarly, the cells
62
A,
62
B and
62
C also have an equal height but mutually different widths, which increase in the order of
62
A<
62
B<
62
C.
Referring back to
FIG. 16
, in arrangement processing S
52
, a plurality of cells are selected from the cell library
53
and two-dimensionally arranged in parallel on a plane based on the circuit designing information
52
. Then, a block layout, including a plurality of cell rows arranged in parallel, is designed. In routing processing S
53
, the cells are wired with each other based on the circuit designing information
52
.
FIG. 18A
illustrates an exemplary block layout designed in accordance with the arrangement processing S
52
and the routing processing S
53
. As shown in
FIG. 18A
, three cell rows
73
a
,
73
b
and
73
c
are arranged in a block
70
. Each of the rows
73
a
,
73
b
and
73
c
includes a plurality of cells
71
. The reference numeral
72
denotes a terminal of the cell
71
and the reference numeral
74
denotes a wire connecting two terminals
72
together. If complete routing cannot be performed only over on-cell regions (i.e., areas directly above the cells), then pure wiring regions
75
a
and
75
b
dedicated entirely for wiring are provided between adjacent rows, and the routing is completed by using these regions
75
a
and
75
b.
FIG. 16
will be referred to again. In cell-in-question extraction processing S
54
, a cell including a circuit section failing to satisfy the required specifications is extracted as a cell to be interchanged with an appropriate cell (in this specification, such a cell will be referred to as a “cell in question”). Herein, assume a delay restriction is imposed on each net. Then, the delay time of each net is calculated based on the delay parameter information of a cell driving the net and a cell at the next stage, which both are included in the cell library
53
, and on the routing results of the routing processing S
53
. If the calculated delay time fails to satisfy the delay restriction, then the cell driving the net is extracted as a cell in question. As shown in
FIG. 18A
, the cell in question is identified by hatching, i.e., a cell
76
A.
In drivability calculation processing S
55
, it is calculated what level of drivability is required for the cell in question, which has been extracted through the cell-in-question extraction processing S
54
, to satisfy the required specifications.
The delay time Td of a net is given by the following equation:
Td=Tin+Tld+Tw+Tp
(1)
where Tin denotes gate intrinsic delay, Tld denotes an over-all load (i.e., a sum of wiring capacitance and the capacitance of the input terminal of a gate on the next stage), Tw denotes wiring delay and Tp denotes delay dependent on the blurred waveform (i.e., a signal having rising and falling edges exhibiting a less sharp shape than the previous signal) of the previous stage.
If the drivability of a cell is varied, then the gate intrinsic delay Tin and the overall load Tld vary but the wiring delay Tw and the delay Tp dependent on the blurred waveform of the previous stage do not vary. The wiring delay Tw is calculated based on the routing designed in accordance with the routing processing S
53
. By using this equation, the drivability of a cell is calculated in such a way that the delay time Td of a net satisfies the restriction thereof.
In cell interchange processing S
56
, the cell in question is replaced with a cell having such a level of drivability as calculated in accordance with the drivability calculation processing S
55
.
The conventional LSI layout designing supposes the use of a cell library
53
such as that shown in FIG.
17
. Thus, if a cell in question is interchanged with a cell having a larger level of drivability, then the substitute cell sometimes overlaps with an adjacent cell, because the cell has a larger cell width. Conversely, if a cell in question is interchanged with a cell having a smaller level of drivability, then a gap is unintentionally produced between the substitute cell and an adjacent cell. In order to eliminate such overlap and gap, some cells belonging to the same row need to be relatively moved in the cell row direction. However, if the cells are moved in such a manner, the terminal positions of the cells are also moved to deviate from the originally intended positions determined in the routing processing S
52
.
FIG. 18B
shows a resultant arrangement in which the cell in question
76
A shown in
FIG. 18A
has been interchanged with a logically equivalent cell
76
B having a larger level of drivability. Since the cell
76
B has a width larger than that of the cell
76
A, the cells located on the right-hand side of the cell
76
B on the same row
73
b
need to be moved to the right in order to prevent the cell
76
B from overlapping the adjacent cell. As a result, the positions of the terminals
72
shown in
FIG. 18B
have also changed by comparison with FIG.
18
A. Also, since the cell row
73
b
becomes longer than that of any other row
73
a
,
73
c
, the resultant width of the block
70
increases and dead spaces, where no cells are disposed, are produced on the right-hand side of the rows
73
a
and
73
c
. The cell-in-question extraction processing S
54
, the drivability calculation processing S
55
and the cell interchange processing S
56
are disclosed, for example, in Shen Lin et al., “Delay and Area optimization in Standard-Cell Design”, 1990 Design Automation Conference, which is herein incorporated by reference.
Referring back to
FIG. 16
, in re-routing processing S
57
, routing is performed again with respect to the terminals moved to different positions.
FIG. 18B
also shows the results of the re-routing processing S
57
. As can be understood from the comparison between
FIGS. 18A and 18B
, the wiring routes have also changed. In this case, the height of the block
70
sometimes changes as a result of the re-routing processing S
57
.
On the other hand, in acc
Fukui Masahiro
Shinomiya Noriko
Everhart Caridad
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Thompson A. M.
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