Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-25
2003-03-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06539529
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and an apparatus for designing integrated circuits, as well as to a storage medium for storing the method. More particularly, the invention relates to a computer-assisted method for designing semiconductor integrated circuits, an apparatus for implementing the method, and a storage medium for storing the method.
Ever-higher operating speeds required of semiconductor integrated circuits have made it increasingly necessary for circuit designs to take into account signal transmission delays (wiring delays) attributable to the parasitic capacities and resistance of wiring. Larger circuit scales and layered layout techniques adopted for circuit fabrication have prolonged wiring patterns, giving rise to a growing number of cases where wiring delays pose a problem in circuit design. Furthermore, processes aimed at fabricating finer circuit structures than ever have tended to increase parasitic capacities between adjacent wires, bringing about crosstalk as another problem in circuit design.
Conventionally, these problems have been bypassed by inserting so-called repeaters in wiring patterns that fail to meet predetermined wiring delay requirements. The repeater is a buffer, such as an inverter or a non-inverter. Inserting repeaters into a wiring pattern reduces the parasitic capacities of the wiring that are driven by a signal output unit of the circuit, whereby signal transmission delays are diminished. Wiring delays are known to increase generally in proportion to the wiring length squared. It follows that a repeater illustratively positioned to bisect a wire at its midpoint cuts the wiring length in half and, thereby, halves the wiring delay provided the delay of the repeater itself is ignored
In a conventional semiconductor integrated circuit design, wiring delays of various wiring patterns are calculated on the basis of known delay-related parameters such as lengths, parasitic capacities and resistances of wiring after the cells and layered blocks constituting the circuit have been laid out. For wiring patterns that fail to meet predetermined wiring delay requirements, parameters regarding locations in which to insert repeaters, including their spacing and their numbers, are automatically calculated. The repeaters are then laid out in the calculated locations.
According to the conventional method above, the automatically calculated locations in which to insert certain repeaters can overlap with cells, layered blocks or other repeaters in the circuit. In many cases, such overlaps prevent the repeaters from being laid out as calculated automatically. Circuit designers are then forced manually to designate in advance desired locations for repeater insertion or to relocate repeaters that overlap with other circuits after automatic layout. Such post-layout chores associated with repeater insertion have tended to prolong the design stage for semiconductor integrated circuits.
The present invention has been made in view of the above circumstances and provides a method and an apparatus for designing semiconductor circuits and a storage medium for storing the method, whereby repeaters are automatically laid out to let wiring patterns meet all wiring delay requirements, so that the repeaters will not overlap with existing circuits, such as cells, layered blocks, and other repeaters.
SUMMARY OF THE INVENTION
In carrying out the invention and according to one aspect thereof, there is provided an integrated circuit designing method including the steps of: firstly, inputting layout data for designating a layout of circuit blocks and wiring patterns constituting an integrated circuit on a substrate, the input layout data serving as a basis for generating layout data such as to let delay adjusting circuits fully occupy, on the substrate, regions which are free of the circuit blocks and ready to accommodate the delay adjusting circuits for adjusting wiring delays between the circuit blocks; secondly, designating locations in which to insert the delay adjusting circuits inside wiring patterns which, among the patterns designated by the input layout data, fail to meet predetermined wiring delay requirements, the locations being designated so that the wiring patterns will meet the delay requirements in conjunction with the inserted delay adjusting circuits; thirdly, selecting from among the delay adjusting circuits designated by the layout data generated in the first step, the delay adjusting circuits that are closest to the locations designated in the second step; fourthly, supplementing data about the connections of the circuit blocks in the input layout data with data about the connections of the delay adjusting circuits selected in the third step; fifthly, removing from the layout data generated in the first step the data about a circuit layout not included in the connection data supplemented in the fourth step; and, sixthly, generating wiring patterns of the integrated circuit based on the connection data supplemented in the fourth step and on the layout data from which the data were removed in the fifth step.
In the first step of the inventive integrated circuit designing method, layout data may be input which designate a layout of circuit blocks and wiring patterns constituting an integrated circuit on a substrate. The input layout data may be used as a basis for generating layout data such as to let delay adjusting circuits fully occupy, on the substrate, regions which are free of the circuit blocks and ready to accommodate the delay adjusting circuits for adjusting wiring delays between the circuit blocks.
In the second step, locations may be designated in which to insert the delay adjusting circuits inside wiring patterns which, among the patterns designated by the input layout data, may fail to meet predetermined wiring delay requirements. These locations may be designated so that the wiring patterns will meet the delay requirements in conjunction with the inserted delay adjusting circuits.
In the third step, the delay adjusting circuits that are closest to the locations designated in the second step may be selected from among the delay adjusting circuits designated by the layout data generated in the first step.
In the fourth step, data about the connections of the circuit blocks in the input layout data may be supplemented with data about the connections of the delay adjusting circuits selected in the third step.
In the fifth step, the data about a circuit layout not included in the connection data supplemented in the fourth step may be removed from the layout data generated in the first step.
In the sixth step, wiring patterns of the integrated circuit may be generated based on the connection data supplemented in the fourth step and on the layout data from which the data were removed in the fifth step.
According to another aspect of the invention, there is provided an integrated circuit designing apparatus including: a layout element for inputting layout data for designating a layout of circuit blocks and wiring patterns constituting an integrated circuit on a substrate, the input layout data serving as a basis for generating layout data such as to let delay adjusting circuits fully occupy, on the substrate, regions which are free of the circuit blocks and ready to accommodate the delay adjusting circuits for adjusting wiring delays between the circuit blocks; an insertion location designating element for designating locations in which to insert the delay adjusting circuits inside wiring patterns which, among the patterns designated by the input layout data, fail to meet predetermined wiring delay requirements, the locations being designated so that the wiring patterns will meet the delay requirements in conjunction with the inserted delay adjusting circuits; a selecting element for selecting, from among the delay adjusting circuits designated by the layout data generated by the layout element, the delay adjusting circuits that are closest to the locations designated by the insertion location designating element; a
Ebisawa Motoji
Inoue Ryouhei
Yamamoto Arata
Kananen, Esq. Ronald P.
Lin Sun James
Rader & Fishman & Grauer, PLLC
Siek Vuthe
Sony Corporation
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