Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-23
2005-08-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06934928
ABSTRACT:
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. Identified problem structures or regions in a pattern of elements are moved from lower level cells of a hierarchy structure into higher level cells before edge movement takes place. Because all cells have been selectively leveled first, substantially all external influences to cells have been removed for each cell before edge movement takes place. The methods and procedures described herein therefore reduce the possibility of undesirable modifications such as electrical shorts. The methods and procedures described herein also reduce overall processing time.
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Dinh Paul
Smith Matthew
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