Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-20
2007-03-20
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10711431
ABSTRACT:
Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to I/O kernels. Since I/O kernels have dedicated power connections, no power busses are present in the depopulated I/O cell sites which can then be freely use for additional core cells, power connections or the like. This technique also allows selection of a chip of minimum required area to be determined prior to design of chip layout.
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Chung-Maloney Wai Ling
Stout Douglas W.
Urish Steven J.
Do Thuan
Kotulak Richard M.
Whitham Curtis Christofferson & Cook PC
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