Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-12-28
2002-07-09
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S206000, C713S100000
Reexamination Certificate
active
06418524
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to computers and more particularly to addressing schemes utilizing segmentation and paging.
BACKGROUND OF THE INVENTION
U.S. Pat. 4,972,338 issued to Crawford et. al. teaches memory management for a microprocessor system. In the microprocessor architecture an address translation unit is included which provides two levels of cache memory management. Segmentation registers and associated segmentation tables in main memory provide a first level of memory management which includes attributes bits for protection, priority, etc. A second page cache memory and associated page directory and page table and main memory provide a second level of management with independent protection on a page level.
To accommodate newer and/or more advanced architectures, a need exists for an addressing scheme that has a dependent relationship between segmentation and paging.
REFERENCES:
patent: 4972338 (1990-11-01), Crawford et al.
patent: 5297282 (1994-03-01), Meilak et al.
patent: 5504801 (1996-04-01), Moser et al.
patent: 5666293 (1997-09-01), Metz et al.
patent: 6178503 (2001-01-01), Madden et al.
Campbell Paul
Dyke Korbin Van
ATI International SRL
Peikari B. James
Vedder Price Kaufman & Kammholz
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