Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-08-25
2002-11-26
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C708S508000
Reexamination Certificate
active
06487653
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of microprocessors and, more particularly, to floating point units within microprocessors.
2. Description of the Related Art
Most microprocessors must support multiple data types. For example, x86-compatible microprocessors must execute two types of instructions; one set defined to operate on integer data types and another set defined to operate on floating point data types. In contrast with integers, floating point numbers have fractional components and are typically represented in exponent-significand format. For example, the values 2.15 and −10.5 are floating point numbers while the numbers −1, 0, and 7 are integers. The term “floating point” is derived from the fact that there is no fixed number of digits before and after the decimal point, i.e., the decimal point can float. Using the same number of bits, the floating point format can represent numbers within a much larger range than integer format. For example, a 32-bit signed integer can represent the integers between −2
31
and 2
31
−1 (using two's complement format). In contrast, a 32-bit (“single precision”) floating point number as defined by the Institute of Electrical and Electronic Engineers (IEEE) Standard 754 has a range (in normalized format) from 2
−126
to 2
127
×(2−2
−23
) in both positive and negative numbers.
FIG. 1
illustrates an exemplary format for an 8-bit integer
100
. As the figure illustrates, negative integers are represented using the two's complement format
106
. To negate an integer, all bits are inverted to obtain the one's complement format
102
. A constant
104
of one is then added to the least significant bit (LSB).
FIG. 2
shows an exemplary format for a floating point value. Value
110
a 32-bit (single precision) floating point number. Value
110
is represented by a significand
112
(23 bits), a biased exponent
114
(8 bits), and a sign bit
116
. The base for the floating point number (2 in this case) is raised to the power of the exponent and multiplied by the significand to arrive at the number represented. In microprocessors, base
2
is most common. The significand comprises a number of bits used to represent the most significant digits of the number. Typically, the significand comprises one bit to the left of the radix point and the remaining bits to the right of the radix point. A number in this form is said to be “normalized”. In order to save space, in some formats the bit to the left of the radix point, known as the integer bit, is not explicitly stored. Instead, it is implied in the format of the number.
Floating point values may also be represented in 64-bit (double precision) or 80-bit (extended precision) format. As with the single precision format, a double precision format value is represented by a significand (52 bits), a biased exponent (11 bits), and a sign bit. An extended precision format value is represented by a significand (64 bits), a biased exponent (15 bits), and a sign bit. However, unlike the other formats, the significand in extended precision includes an explicit integer bit. Additional information regarding floating point number formats may be obtained in IEEE Standard 754.
When a numeric value approaches zero, normalized floating-point format may not be able to express the value accurately. To accommodate these instances, x86-compatible microprocessors support a “denormal” format in which the significand contains one or more leading zeros. Denormal values have biased exponents fixed at their smallest possible value (i.e., zero). The leading zeros of denormals permit smaller numbers to be represented.
FIG. 3
shows a denormal value
130
in single precision format. As the figure illustrates, denormal values have a biased exponent
134
equal to zero and a non-zero significand
132
. Denormals may be positive or negative (as indicated by sign bit
136
).
Microprocessors that are x86 compatible and support floating point instructions must be able to load, store, and operate on denormalized real numbers. This presents several problems for microprocessor designers. One problem in particular relates to loading and manipulating the denormal value in the floating point unit. To improve performance, microprocessors are typically designed with a number of “execution units” that are each optimized to perform a particular set of functions or instructions on a particular data type. For example, one or more execution units within a microprocessor may be optimized to perform arithmetic functions on integer values, while a second set of execution units may be optimized to perform arithmetic functions on floating point values. These floating point execution units (combined with their supporting control logic) may be collectively referred to as the microprocessor's “floating point unit”.
Most floating point units translate floating point numbers into a processor-specific internal format before the numbers are operated upon. Using one format for all internal floating point calculations advantageously reduces the complexity of the floating point unit's execution units.
FIG. 4
shows one possible internal floating point format
170
comprising a 68-bit significand
172
, an 18-bit biased exponent
174
, and a sign bit
176
. The use of a single internal floating point format tends to simplify the hardware used to implement the floating point unit. For example, instead of having to process three different formats (i.e., single-precision, double-precision, and extended precision), the floating point processor may translate all floating point values into extended precision format or an internal format. Once the desired operations have been performed, the results are then translated back to the desired format.
The problem denormal values pose to designers relates to translating denormals into this internal format. Normal values may be translated by simply shifting in constant zeros and adjusting the exponent. This conversion process may be performed in a single clock cycle. With denormals, however, the conversion process takes longer because the number must be normalized after the constants are shifted in. For example, in some microprocessors at least two clock cycles are needed to convert the denormal to a normalized internal format.
Since the number of clock cycles needed to process normals and denormals varies, designers are left with a quandary. The designers can make all loads take two clock cycles, but this is undesirable because normal loads are more common than denormal loads. Thus, overall microprocessor performance may suffer due to the unnecessary additional latency incorporated into normal loads.
Another alternative that has been used by designers is to detect the denormal, stall the pipeline, and then trap to microcode to convert the denormal. Yet another alternative is to tag the denormal and then convert it later when it reaches an execution unit. However, these solutions are slow (i.e., the original instruction may need to be re-executed after the denormal is converted) and may reduce the throughput of floating point operations when even a few denormal loads are experienced. Thus an efficient method for rapidly handling denormal loads is desired.
SUMMARY
The problems outlined above may at least in part be solved by a microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length. In one embodiment, the microprocessor may accomplish this by performing normal loads and detect denormal loads in a single clock cycle. The microprocessor may temporarily store each floating point instruction in a reissue buffer for at least one clock cycle in anticipation of a denormal load. When a denormal load is detected, the microprocessor is configured to add one or more stages to the floating point load pipeline (e.g., adding a normalization stage to the conversion stage) to allow the denormal value to complete the conver
Meier Stephan G.
Oberman Stuart F.
Trull Jeffrey E.
Advanced Micro Devices , Inc.
Coleman Eric
Conley Rose & Tayon PC
Kivlin B. Noäl
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