Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-08-30
2005-08-30
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S143000, C711S150000, C711S151000, C711S156000, C711S158000, C711S130000, C710S264000, C710S263000, C710S261000, C710S240000, C710S244000, C718S102000
Reexamination Certificate
active
06938130
ABSTRACT:
One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.
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Chaudhry Shailender
Jacobson Quinn A.
Tremblay Marc
Kim Hong
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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