Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-07-30
2003-05-13
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000
Reexamination Certificate
active
06564299
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to addressable circuits, and to the definition of an addressable range therefor. For example, the invention may find application to digital caches, memory management units (MMU's), paging units, chip-select decoders, write buffers, and other circuits which require an addressable range to be controllably defined.
BACKGROUND TO THE INVENTION
FIG. 1
illustrates a typical, conventional arrangement of a cache
10
in a digital processing system. The cache
10
is interposed between a main processor (CPU)
12
and a peripheral bus
14
for communicating with addressable system resources, such as memory
16
and one or more peripherals
18
. The cache
10
contains its own fast access memory, which is used to buffer data (ideally the most frequently accessed data) which would normally be accessed over the peripheral bus
14
. When the CPU requests an access which can be handled by the cache
10
(referred to as a cache-hit), the cache
10
services the access and suspends the access to the peripheral bus
14
. Since the cache can service the access more rapidly than the other devices, the system performance is improved.
It is conventional in the art for the cache
10
to include a plurality of configuration registers for defining the range or ranges of addresses which are cacheable, rather than treating all addresses as cacheable. There are many situations in which the cache
10
should be prevented from buffering certain areas of the address range. For example, direct memory-mapped input and/our output (MMIO) addresses for peripherals should not be cached (if they were, during a read-access the cache would return previously buffered data rather than the actual live data from the peripheral; during a write-access, the cache would intercept the data, and possibly delay the writing of the data to the peripheral). Similarly, if a resource is accessible to a plurality of master devices, then the resource address should not be cached, because the cache may not contain the current data for the resource (e.g., if the cache is written to by one master, and read by another). A further situation is if a particular resource is as fast as the cache (e.g., fast memory). In that case, it would be a waste of cache resources to cache the address of the fast resource, since this would not improve system performance.
FIG. 2
illustrates schematically the format of conventional configuration registers
20
in the cache
10
. There are a fixed number of registers
20
(e.g., six registers), and each register defines a sub-range of cacheable addresses by means of a base address or start address field
22
and a size field
24
. The register also includes an enable flag field
26
which determines whether the register is enabled. If the register is disabled, then the contents are ignored (so as not to define an incorrect area if not all six registers are needed to define the cacheable area).
In order to simplify the cache logic, and to ensure speedy operation, certain limitations are applied to the definitions of cacheable addresses in the configuration registers. Firstly, instead of treating addresses on an individual basis, the address ranges are defined in terms of blocks of a certain unit size, such as 4 KB. This is also referred to as the granularity of the cacheable address definitions. Both the start address field
22
and the size field
24
are defined either as, or to be, integer multiples of the granularity unit. Concerning the size, the factor by which the granularity unit is multiplied must furthermore be a power of two. Additionally, the start address is limited to being an integer multiple of the size. Therefore, if the size is 8 KB, then the start address can only be 0, 8 KB, 16 KB, etc. These limitations make the address ranges easier to process.
The sum of valid addressable areas defined by the configuration registers makes up the total cacheable area. This is then used in the address-path logic of the cache. When a CPU-access reaches the cache, the incoming address is compared with all of the single memory areas simultaneously. Only if the incoming address lies within any cacheable area defined by a configuration register, is the request serviceable by the cache. Otherwise, the cache suppresses the “hit”, and forwards the access to the peripheral bus
14
.
FIG. 3
illustrates by way of example a memory map showing the definition of cacheable areas (dark or patterned areas) by six configuration registers (
1
-
6
). In this example, the address range is 0-65535 (16 bit address), and the granularity is 4 KB, such that the address range is divided into 16 blocks (0-15), each of 4 KB. In the illustrated example, all six registers are required to define the illustrated net cacheable range denoted by 30. In particular, two registers are required to define the adjacent 2-blocks defined by configurations registers
2
and
3
, since the first block starts at an “odd” address. (If the first block had started at an even address, then the two blocks could have been defined by a single configuration register).
Also, it would be impossible to define a range such as that denoted by 32 (including an additional cacheable block
34
), since an additional (seventh) configuration register would be needed to define the block
34
.
SUMMARY OF THE INVENTION
The present invention concerns an addressable circuit configured to control the definition of an addressable range for the circuit. The circuit may comprise at least one register, at east one flag, an input and control logic. The register may be configured to define a range used for determining an addressable range for the circuit. The flag may be configured to define whether a predetermined range is to be inverted for determining the addressable range for the circuit. The input may be configured to receive an address for an access to the circuit. The control logic may be configured to process the received address to determine whether the received address is within the addressable range for the circuit, the control logic being responsive to the register and to the flag for determining the addressable range therefrom.
The objects, features and advantages of the present invention include providing an addressable circuit that may (i) have a versatile way of defining an addressable range, and which can be compatible with existing controls, (ii) provide flexibility in a definition of an addressable range, (iii) enable a reduction in the number of configuration registers needed to define a certain address range and/or (iv) enable ranges to be defined which hitherto were not possible using a limited number of configuration registers.
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LSI Logic Corporation
Maiorana PC Christopher P.
Verbrugge Kevin
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