Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2006-08-22
2006-08-22
Elamin, Abdelmoniem (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S320000, C713S321000, C713S322000, C713S324000, C713S300000, C713S330000, C713S340000
Reexamination Certificate
active
07096374
ABSTRACT:
The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. The digital circuit includes one or more circuit elements of respective circuit element types. In the method, idle power values including idle power values for each circuit element type. The idle power values for each circuit element type correspond to different states of the inputs of a circuit element of the circuit element type. Additionally the idle power values are used to determine, for each circuit element, states of the inputs of the circuit element that would set the circuit element to a lowest-allowable idle power state when the digital circuit is in the idle state. The states determined for those of the inputs that constitute the circuit inputs define the input state vector. The states are also determined accounting for the logic constraints of the digital circuit.
REFERENCES:
patent: 6175245 (2001-01-01), Bowe et al.
patent: 6175938 (2001-01-01), Hsu
patent: 6216246 (2001-04-01), Shau
patent: 6449204 (2002-09-01), Arimoto et al.
patent: 6617916 (2003-09-01), Kurotsu
patent: 6643166 (2003-11-01), Ting et al.
patent: 6925002 (2005-08-01), Arimoto et al.
patent: 6940777 (2005-09-01), Ooishi
patent: 2003/0103368 (2003-06-01), Arimoto et al.
patent: 2004/0085845 (2004-05-01), Ooishi
Johnson, Mark C., “Models and Algorithms for Bounds on Leakage in CMOS Circuits”, IEEE Transactions on Computer-Aided Design . . . , vol. 18, No. 6, Jun. 1999, pp. 714-725.
Halter, Jonathan P. et al., “A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Clrcuits”, IEEE 1997 Custom Integrated Circuits Conference, pp. 475-478.
Guindi, Rafik et al., “Design Techniques for Gate-Leakage Reduction in CMOS Circuits”, Proceedings of the Fourth Intl. Symposium on Quality Electronic Design, IEEE 2003.
Rao, Rahul M. et al., “A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits”, IEEE/AM Intl. Cinference on Computer Aided Design, Nov. 2003, pp. 689-692.
Naidu S. R. et al., “Minimizing Stand-By Leakage Power in Static CMOS Circuits”, Design, Automation & Test in Europe, Mar. 2001,.
Abdollahi, A. et al., “Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits”, Low Power Electronics and Design, Aug. 2002, pp. 213-218.
Aloul, F. A. et al. “Robust SAT-based Search Algorithm for Leakage Power Reduction”, Integrated Circuit Design, 2002, pp. 167-168.
Chen, Zhanping et al., “Estimation of Standby Leakage Power in CMOS Circuit . . . ”, 1998 Intl Symposium on Low Power ELectronics . . . , 1998, pp. 239-244.
Kopley Thomas E.
Srikantam Vamsi K.
Agilent Technologie,s Inc.
Elamin Abdelmoniem
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